Patents by Inventor Yoshihiro Nakata

Yoshihiro Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8716209
    Abstract: The invention provides an agent for post-etch treating a silicon dielectric film, including: at least one nitrogen-containing substance selected from the group consisting of ammonium bases and amine compounds; an acid; and at least one silicon-containing compound containing silicon, carbon and hydrogen. According to the present invention, it becomes possible to suppress an increase in the dielectric constant of a silicon dielectric film caused by etching.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasushi Kobayashi, Kouta Yoshikawa, Yoshihiro Nakata, Tadahiro Imada, Shirou Ozaki
  • Publication number: 20140042833
    Abstract: A linear vernier motor includes a stator and a mover. The stator extends in a first direction. The mover extends in the first direction and a pole interval is different from that of the stator. At least one of the stator and the mover includes: a plurality of permanent magnets arranged in the first direction and a plurality of yokes arranged in the first direction. Each of the plurality of yokes is arranged between adjacent permanent magnets. The plurality of permanent magnets is magnetized to the first direction and magnetization orientations of adjacent permanent magnets are opposite to each other.
    Type: Application
    Filed: May 16, 2012
    Publication date: February 13, 2014
    Inventors: Ryota Hiura, Katsuhiro Hirata, Hiroshi Ishiguro, Yoshihiro Nakata
  • Patent number: 8580907
    Abstract: An insulating film material, which contains a polycarbosilane compound expressed by the following structural formula 1: where R1 may be the same or different to each other in the unit repeated “n” times, and each represents C1-4 hydrocarbon or aromatic hydrocarbon; R2 may be the same or different to each other in the unit repeated “n” times, and each represents C1-4 hydrocarbon or aromatic hydrocarbon; n is an integer of 5 to 5,000.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Yasushi Kobayashi, Yoshihiro Nakata, Shirou Ozaki
  • Publication number: 20130233489
    Abstract: A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 12, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Yoshihiro Nakata, Koji Nozaki
  • Patent number: 8461041
    Abstract: The method of manufacturing a semiconductor device includes forming an insulating film of a silicon compound-group insulation film; forming an opening in the insulation film, applying an active energy beam in an atmosphere containing hydrocarbon gas to form a barrier layer of a crystalline SiC, and forming an interconnection structure of copper in the opening with the barrier layer formed in.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 11, 2013
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Yasushi Kobayashi, Yuichi Minoura
  • Patent number: 8449787
    Abstract: A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: May 28, 2013
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata, Koji Nozaki
  • Patent number: 8440577
    Abstract: To provide a reliable, efficient method for reducing oxidized metals used upon manufacturing of the multilayer interconnection structure, semiconductor device, etc. With this method vapor containing at least a carboxylic acid ester is hydrolyzed by water vapor to reduce oxidized metal. The multilayer interconnection manufacturing method of the present invention includes at least film formation step, interconnection formation step, and reduction step using the metal reduction method of the present invention. The multilayer interconnection structure of the present invention is manufactured by the multilayer interconnection structure manufacturing method of the present invention. The semiconductor device manufacturing method of the present invention includes at least film formation step, patterning step, interconnection formation step, and reduction step using the metal reduction method.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: May 14, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Nakata
  • Patent number: 8431464
    Abstract: A silicic coating of 2.4 g/cm3 or higher density, obtained by forming a silicic coating precursor with the use of at least one type of silane compound having a photosensitive functional group and thereafter irradiating the silicic coating precursor with at least one type of light. This silicic coating can be used as a novel barrier film or stopper film for semiconductor device.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: April 30, 2013
    Assignee: Fujitsu Limited
    Inventors: Yasushi Kobayashi, Kouta Yoshikawa, Yoshihiro Nakata, Tadahiro Imada, Shirou Ozaki
  • Patent number: 8399295
    Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: March 19, 2013
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
  • Patent number: 8390099
    Abstract: An interconnection substrate including: a first insulating film made of a silicon compound, an adhesion enhancing layer formed on the first insulating film, and a second insulting film made of a silicon compound and formed on the adhesion enhancing layer, wherein the first insulating film and the second insulating film are combined together with a component having a structure represented by General Formula (1) described below: Si—CXHY—Si??General Formula (1) where y is equal to 2x and is an even integer.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: March 5, 2013
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Tadahiro Imada, Yasushi Kobayashi
  • Publication number: 20130048358
    Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: February 28, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi KANKI, Shoichi Suda, Yoshihiro Nakata
  • Patent number: 8382352
    Abstract: Disclosed is a projector-type headlight that can include a light emitting device, a reflector having a reflection surface to reflect a light from the light emitting device forward, a projector lens to project the reflected light from the reflection surface forward, the projector lens being a resin molding, and a shade to form a light distribution pattern having a light-dark border line by blocking a part of the reflected light heading from the reflection surface to the projector lens. A gate trace can be formed in a circumference portion of the projector lens. The gate trace can be provided lower than a horizontal surface on which a light axis of the projector lens passes through, and at the same time can be provided in a state of being shifted either leftward or rightward from a vertical surface on which the light axis of the projector lens passes through.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: February 26, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasushi Yatsuda, Yoshihiro Nakata, Eiji Kawamoto
  • Patent number: 8378489
    Abstract: A semiconductor device of this invention has a copper wiring layer, of which a layer, to which a composition including at least one substance selected from the group consisting of ammonia and organic bases is applied, and a silicon-containing insulating film are sequentially superimposed on the copper wiring layer. Accordingly, semiconductor devices having insulating layers which adheres well to the copper serving as the wiring material can be obtained.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 19, 2013
    Assignee: Fujitsu Limited
    Inventors: Shiro Ozaki, Yoshihiro Nakata, Yasushi Kobayashi, Ei Yano
  • Publication number: 20120325920
    Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.
    Type: Application
    Filed: September 10, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Publication number: 20120181070
    Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
    Type: Application
    Filed: March 27, 2012
    Publication date: July 19, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
  • Patent number: 8207059
    Abstract: A layer of a porous insulating film precursor is formed on or over a substrate, a layer of a specific silicon compound is then formed, this silicon compound layer is pre-cured as necessary, and the porous insulating film precursor is exposed to UV through the silicon compound layer or pre-cured layer.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 26, 2012
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
  • Patent number: 8164166
    Abstract: An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that comprises at least one bond of Si—N bonds and Si—Cl bonds wherein the number of Si—N bonds and Si—Cl bonds combined per molecule of the compound is at least two. An interfacial roughness between the interfacial roughness reducing film and the wiring is smaller than that between the interfacial roughness reducing film and the insulating film.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata, Kouta Yoshikawa
  • Patent number: 8124239
    Abstract: The silica film forming material of the present invention comprises a silicone polymer which comprises, as part of its structure, CHx, an Si—O—Si bond, an Si—CH3 bond and an Si—CHx- bond, where x represents an integer of 0 to 2.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 28, 2012
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Ei Yano
  • Patent number: 8089138
    Abstract: A surface-hydrophobicized film is provided which is in contact with an insulating film, and has a higher hydrophobicity than the insulating film at the time of the contact, and which is in contact, on an opposite side of the surface-hydrophobicized film, with wiring, and contains at least one atom selected from the group consisting of sulfur atoms, phosphorus atoms and nitrogen atoms. Semiconductor devices with wiring layers having a low leakage current, a high EM resistance and a high TDDB resistance can be manufactured by using the film.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata
  • Patent number: 8062414
    Abstract: The present invention relates to a coating liquid for forming an amorphous silica-based coating film with a low dielectric constant of 2.5 or below and the Young's modulus of 6.0 GPa or more and having excellent hydrophobic property, and to a method of preparing the same. The coating liquid may contain a silicon compound obtained by hydrolyzing tetraalkyl ortho silicate (TAOS) and specific alkoxysilane (AS) in the presence of tetraalkyl ammonium hydroxide (TAAOH), or may contain a silicon compound obtained by hydrolyzing or partially hydrolyzing tetraalkyl ortho silicate (TAOS) in the presence of tetraalkyl ammonium hydroxide (TAAOH), mixing the reaction product with specific alkoxysilane or a hydrolysate or a partial hydrolysate thereof, and hydrolyzing all or a portion of the mixture according to the necessity. In addition, the coating liquid is prepared by mixing components described above at a specific ratio and under specific process conditions.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: November 22, 2011
    Assignees: JGC Catalysts and Chemicals Ltd., Fujitsu Limited
    Inventors: Akira Nakashima, Miki Egami, Michio Komatsu, Yoshihiro Nakata, Ei Yano, Katsumi Suzuki