Patents by Inventor Yoshihiro Nonaka
Yoshihiro Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150379924Abstract: In a pixel array in which rectangular pixels, each enclosing a subpixel of the first color (SP1) which has the highest luminosity factor, a subpixel of the second color (SP2) and a subpixel of the third color (SP3) which has the lowest luminosity factor, are two-dimensionally arranged, SP2 includes first and second portions respectively near two corners adjacent to each other in the first direction of the pixel, SP3 includes first and second portions near other two corners adjacent each other in the first direction of the rectangular pixel, and SP1 is located at a middle part including a center of gravity of the rectangular pixel. SP3 has a larger area than each of SP1 and SP2. In the second direction orthogonal to the first direction, SP2 and SP3 are widest near a pixel boundary in the first direction, SP1 is widest near the center of gravity in the pixel.Type: ApplicationFiled: June 24, 2015Publication date: December 31, 2015Inventors: Yojiro MATSUEDA, Kenichi TAKATORI, Yoshihiro NONAKA
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Publication number: 20150311265Abstract: There are provided a pixel array, an electro-optic device, and an electric apparatus. A pixel array includes plural pixels each having a rectangular shape and including a first-colored sub-pixel of a first color being the maximum in relative luminosity, a second-colored sub-pixel, and a third-colored sub-pixel of a third color being the minimum in relative luminosity. The third-colored sub-pixel is greater in size than each of the first-colored sub-pixel and the second-colored sub-pixel, and is arranged next to the first-colored sub-pixel and the second-colored sub-pixel. The center of gravity of the first-colored sub-pixel is located nearer to the center of gravity of the pixel than that of the second-colored sub-pixels, and/or the center of gravity of a part of the third-colored sub-pixel at the second-colored-sub-pixel side is located at a shorter distance to the center of gravity of the pixel than that of the other part of the third-colored sub-pixel.Type: ApplicationFiled: April 20, 2015Publication date: October 29, 2015Inventors: Yojiro MATSUEDA, Kenichi TAKATORI, Yoshihiro NONAKA
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Publication number: 20150177980Abstract: A touch sensor device includes: an impedance surface where plural sets of reference coordinates are set at plural locations; plural detection electrodes arranged on the impedance surface; a detection circuit configured to detect electric currents passing the detection electrodes; a storage section storing reference standardized values and reference normalized values; a position coordinate calculation section configured to obtain standardized values calculated by standardizing the electric currents detected in each detection period and to map the standardized values onto position coordinates; a first normalized value calculation section configured to map the position coordinates onto first normalized values; a second normalized value calculation section configured to calculate second normalized values by normalizing the electric currents in each detection period; and a touch gesture detection section configured to detect a motion of pointers on the basis of a time variation of the first normalized values and tType: ApplicationFiled: December 22, 2014Publication date: June 25, 2015Applicant: NLT TECHNOLOGIES, LTD.Inventors: Jiro YANASE, Yoshihiro NONAKA
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Patent number: 8711317Abstract: Provided is a color filter substrate including: an end portion unit pixel including a plurality of kinds of end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship; and an inner unit pixel including a plurality of kinds of inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship, wherein a relative area proportion of the end portion sub-pixels is set equal to that of the inner sub-pixels; and wherein the plurality of kinds of the end portion sub-pixels is arrayed in accordance with a position or a shape on an outer edge of the display region, an array direction of the plurality of kinds of the end portion sub-pixels and an array direction of the plurality of kinds of the inner sub-pixels configured to intersect each other.Type: GrantFiled: April 19, 2013Date of Patent: April 29, 2014Assignee: NLT Technologies, Ltd.Inventor: Yoshihiro Nonaka
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Patent number: 8681084Abstract: A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.Type: GrantFiled: September 19, 2005Date of Patent: March 25, 2014Assignee: Gold Charm LimitedInventors: Hiroshi Haga, Tomohiko Otose, Hideki Asada, Yoshihiro Nonaka, Takahiro Korenari, Kenichi Takatori
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Patent number: 8638280Abstract: Disclosed is a display apparatus comprising an active matrix display section including a plurality of signal lines and scan lines, arranged in a matrix on a substrate, and a plurality of pixels and active elements arranged at intersections of the signal and scan lines, a scan line driving circuit for driving the scan lines and a signal line driving circuit for driving the signal lines. The display section has a non-rectangular shape. The active elements that make up the scan line driving circuit and/or the signal line driving circuit are formed by the same manufacturing process as that for forming the active elements in the active matrix display section. The scan line driving circuit and/or the signal line driving circuit are each a set of circuit units having the same function. These circuit units are arranged to conform to and extend around the outer circumference of the non-rectangular display section.Type: GrantFiled: April 25, 2008Date of Patent: January 28, 2014Assignee: NLT Technologies, Ltd.Inventor: Yoshihiro Nonaka
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Publication number: 20130300965Abstract: Provided is a color filter substrate including: an end portion unit pixel including a plurality of kinds of end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship; and an inner unit pixel including a plurality of kinds of inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship, wherein a relative area proportion of the end portion sub-pixels is set equal to that of the inner sub-pixels; and wherein the plurality of kinds of the end portion sub-pixels is arrayed in accordance with a position or a shape on an outer edge of the display region, an array direction of the plurality of kinds of the end portion sub-pixels and an array direction of the plurality of kinds of the inner sub-pixels configured to intersect each other.Type: ApplicationFiled: April 19, 2013Publication date: November 14, 2013Inventor: Yoshihiro NONAKA
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Patent number: 8451414Abstract: A color image display device is provided which is capable of displaying an image with no differences in color balance between end portions and inner portions of anon-rectangle image display region. The color image display device includes an end portion unit pixel formed in an edge portion of a display region in which a color image is displayed and including end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship and an inner unit pixel formed in an inside of the display region with respect to the end portion unit pixels and including inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship. With such a configuration, a relative area proportion of the end portion sub-pixels that correspond to the primary colors respectively in a one-to-one relationship is set equal to that of the inner sub-pixels that correspond to the primary colors respectively in a one-to-one relationship.Type: GrantFiled: May 12, 2010Date of Patent: May 28, 2013Assignee: NLT Technologies, Ltd.Inventor: Yoshihiro Nonaka
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Patent number: 8269547Abstract: A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.Type: GrantFiled: September 1, 2010Date of Patent: September 18, 2012Assignee: NLT Technologies, Ltd.Inventor: Yoshihiro Nonaka
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Patent number: 8264476Abstract: The present invention relates to a semiconductor device in which a power supply circuit is disposed on an array substrate, which achieves reduction of the size by suppressing an increase of the area occupied by the power supply wiring. The feature of the present invention is that a power supply circuit is disposed adjacent to a supply voltage input terminal and a signal line driving circuit. An extremely large amount of electric current is flown in a power supply wiring between the power supply circuit and the supply voltage input terminal and a power supply wiring between the power supply circuit and the signal line driving circuit. Thus, by disposing the power supply circuit adjacent to the supply voltage input terminal and the signal line driving circuit, the power supply wirings therebetween can be shortened. Accordingly, the wiring resistance proportional to the product of the length and the width becomes small so that the thinned power supply wiring can be tolerated.Type: GrantFiled: February 11, 2005Date of Patent: September 11, 2012Assignee: NLT Technologies, Ltd.Inventor: Yoshihiro Nonaka
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Publication number: 20110050317Abstract: A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.Type: ApplicationFiled: September 1, 2010Publication date: March 3, 2011Applicant: NEC LCD Technologies, Ltd.Inventor: Yoshihiro NONAKA
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Publication number: 20100289994Abstract: A color image display device is provided which is capable of displaying an image with no differences in color balance between end portions and inner portions of anon-rectangle image display region. The color image display device includes an end portion unit pixel formed in an edge portion of a display region in which a color image is displayed and including end portion sub-pixels which correspond to a plurality of kinds of primary colors respectively in a one-to-one relationship and an inner unit pixel formed in an inside of the display region with respect to the end portion unit pixels and including inner sub-pixels which correspond to the plurality of kinds of primary colors respectively in a one-to-one relationship. With such a configuration, a relative area proportion of the end portion sub-pixels that correspond to the primary colors respectively in a one-to-one relationship is set equal to that of the inner sub-pixels that correspond to the primary colors respectively in a one-to-one relationship.Type: ApplicationFiled: May 12, 2010Publication date: November 18, 2010Applicant: NEC LCD TECHNOLOGIES, LTD.Inventor: Yoshihiro Nonaka
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Patent number: 7719063Abstract: A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region.Type: GrantFiled: April 21, 2008Date of Patent: May 18, 2010Assignee: NEC CorporationInventor: Yoshihiro Nonaka
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Patent number: 7564297Abstract: A power supply circuit is provided which is capable of preventing a drop in an output voltage of the power supply circuit used as a DC/DC converter made up of single and conductive type (n-type or p-type) MOS transistors and of improving efficiency. Since a control voltage having an amplitude [2×VDD] is applied from a level shift circuit to a charge-pump circuit, even when potentials at nodes becomes a level [2×VDD], pMOS transistors are kept in an OFF state, thereby preventing leakage of currents from pMOS transistors. This avoids a drop in an DC output voltage. As inputs to the level shift circuits, potentials at nodes of the charge-pump circuit are used and, therefore, even if potentials at nodes of the level shift circuits are high, pMOS transistors are kept in an OFF state.Type: GrantFiled: August 21, 2007Date of Patent: July 21, 2009Assignee: NEC LCD Technologies, LtdInventor: Yoshihiro Nonaka
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Patent number: 7518407Abstract: A bootstrap circuit includes an output transistor, a bootstrap capacitor provided between the gate and source of the output transistor, a power source, and a circuit that performs ON/OFF control of a supply from the power source to the gate electrode of the transistor. An initial voltage before a bootstrap effect can be set to the potential of the power source, which is independent of the threshold voltage of the transistor. Therefore, the source output of the transistor rising or dropping due to the bootstrap effect is not affected by variations that depend on the threshold voltage of the transistor.Type: GrantFiled: November 16, 2005Date of Patent: April 14, 2009Assignee: NEC CorporationInventor: Yoshihiro Nonaka
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Publication number: 20080266210Abstract: Disclosed is a display apparatus comprising an active matrix display section including a plurality of signal lines and scan lines, arranged in a matrix on a substrate, and a plurality of pixels and active elements arranged at intersections of the signal and scan lines, a scan line driving circuit for driving the scan lines and a signal line driving circuit for driving the signal lines. The display section has a non-rectangular shape. The active elements that make up the scan line driving circuit and/or the signal line driving circuit are formed by the same manufacturing process as that for forming the active elements in the active matrix display section. The scan line driving circuit and/or the signal line driving circuit are each a set of circuit units having the same function. These circuit units are arranged to conform to and extend around the outer circumference of the non-rectangular display section.Type: ApplicationFiled: April 25, 2008Publication date: October 30, 2008Applicant: NEC LCD TECHNOLOGIES, LTDInventor: Yoshihiro NONAKA
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Publication number: 20080203439Abstract: A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region.Type: ApplicationFiled: April 21, 2008Publication date: August 28, 2008Applicant: NEC CORPORATIONInventor: Yoshihiro Nonaka
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Patent number: 7376923Abstract: A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes.Type: GrantFiled: September 8, 2006Date of Patent: May 20, 2008Assignee: NEC CorporationInventor: Yoshihiro Nonaka
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Publication number: 20080048765Abstract: A power supply circuit is provided which is capable of preventing a drop in an output voltage of the power supply circuit used as a DC/DC converter made up of single and conductive type (n-type or p-type) MOS transistors and of improving efficiency. Since a control voltage having an amplitude [2×VDD] is applied from a level shift circuit to a charge-pump circuit, even when potentials at nodes becomes a level [2×VDD], pMOS transistors are kept in an OFF state, thereby preventing leakage of currents from pMOS transistors. This avoids a drop in an DC output voltage. As inputs to the level shift circuits, potentials at nodes of the charge-pump circuit are used and, therefore, even if potentials at nodes of the level shift circuits are high, pMOS transistors are kept in an OFF state.Type: ApplicationFiled: August 21, 2007Publication date: February 28, 2008Applicant: NEC LCD TECHNOLOGIES, LTD.Inventor: Yoshihiro NONAKA
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Patent number: 7294891Abstract: A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes.Type: GrantFiled: August 27, 2003Date of Patent: November 13, 2007Assignee: NEC CorporationInventor: Yoshihiro Nonaka