Patents by Inventor Yoshihiro Saeki
Yoshihiro Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110169376Abstract: An SIDM device 1 is provided with a columnar piezoelectric element 2 which expands and contracts in the axial direction by the application of a voltage, a columnar-shaped driving rod 3 which is fixed to the end surface of the piezoelectric element 2 in the axial direction and is displaced by the expiation and contraction of the piezoelectric element 2, a supporting member 4 which has a fixed portion 40 fixed to the driving rod 3 and supports the piezoelectric element 2 and the driving rod 3 with the fixed portion 40 between the supporting member 4, and the piezoelectric element 2 and the driving rod 3, and a moving body 5 which is frictionally engaged with the driving rod 3 and moves in the axial direction of the driving rod 3. A central axis L2 of the piezoelectric element 2 and a central axis L3 of the driving rod 3 are offset to each other, and the central axis L3 of the driving rod 3 and a central axis L4 of the driving rod 3 in the axial direction in the entire fixed portion 40 are offset to each other.Type: ApplicationFiled: September 3, 2009Publication date: July 14, 2011Inventors: Junichiro Yonetake, Yoshihiro Saeki, Kazuhiro Shibatani
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Publication number: 20100320581Abstract: The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.Type: ApplicationFiled: August 24, 2010Publication date: December 23, 2010Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Yoshihiro Saeki
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Publication number: 20100248450Abstract: A method of producing a semiconductor device includes: a dicing step of dicing a wafer member using a dicing blade to form a cut portion in the wafer member, in which the wafer member is formed of a wafer portion, a glass substrate, and an adhesive layer for bonding the wafer portion and the glass substrate in a thickness direction of the wafer member so that the cut portion penetrates the wafer portion and the adhesive layer and reaches a part of the glass substrate; and an individual piece dividing step of dividing the wafer member into a plurality of semiconductor devices with the cut portion as a fracture initiation portion.Type: ApplicationFiled: March 17, 2010Publication date: September 30, 2010Inventor: Yoshihiro SAEKI
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Patent number: 7804161Abstract: The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.Type: GrantFiled: March 6, 2008Date of Patent: September 28, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 7679175Abstract: A semiconductor device includes a lower substrate having at least one wiring pattern formed of a plurality of wirings, a semiconductor chip positioned above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chip in columnar form and substantially, and an upper plate which substantially covers a whole upper surface of the intermediate member. A thermal expansion coefficient of the upper plate and a thermal expansion coefficient of the lower substrate are set substantially identical.Type: GrantFiled: March 23, 2006Date of Patent: March 16, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 7662671Abstract: A method of manufacturing a semiconductor device is disclosed, which includes at least the steps of preparing a laminated structure including a single chip or a plurality of chips, and dividing the laminated structure into a plurality of sub-laminated structures. A laminated structure comprised of a silicon substrate and a single chip or a plurality of chips laminated on the silicon substrate is formed. Then, the laminated structure is divided into a plurality of sub-laminated structures. Each of the sub-laminated structures includes a semiconductor device.Type: GrantFiled: September 14, 2006Date of Patent: February 16, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 7614301Abstract: An acceleration sensor chip package includes an acceleration sensor chip formed of a frame portion with an opening portion, a movable structure, a detection element, and an electrode pad. The movable structure has a beam portion and a movable portion supported on the beam portion to be movable. The acceleration sensor chip package further includes a re-wiring layer with a wiring portion having one end connected to the electrode pad; an outer terminal connected to the other end of the wiring portion; a first sealing portion for sealing the electrode pad and the re-wiring layer; and a substrate for sealing the opening portion of the frame portion.Type: GrantFiled: October 18, 2007Date of Patent: November 10, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Publication number: 20090155953Abstract: Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions.Type: ApplicationFiled: December 4, 2008Publication date: June 18, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Yoshihiro Saeki
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Patent number: 7514796Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.Type: GrantFiled: November 3, 2006Date of Patent: April 7, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 7492038Abstract: A semiconductor device according to the present invention comprises, on a first semiconductor chip, a first circuit element region in which a first electrode group is arranged along an outer periphery of the first semiconductor chip in such a manner as to surround a second semiconductor chip, a second electrode group is arranged along the outer periphery of the first semiconductor chip in such a manner as to surround the first electrode group, and the first semiconductor chip is surrounded by the first electrode group, and a second circuit element region which surrounds the first electrode group and is surrounded by the second electrode group.Type: GrantFiled: January 21, 2004Date of Patent: February 17, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Yoshihiro Saeki, Shinji Hiratsuka, Daigo Chabata
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Publication number: 20090031563Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.Type: ApplicationFiled: May 20, 2008Publication date: February 5, 2009Inventors: Yasufumi Uchida, Yoshihiro Saeki
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Patent number: 7459348Abstract: A method for manufacturing a semiconductor device formed by stacking a plurality of semiconductor elements on a substrate includes the steps of stacking the plurality of semiconductor elements on the substrate to form plural stages, placing the substrate substantially vertically and charging an underfill agent into spaces defined between the substrate and the corresponding semiconductor element and spaces defined among the stacked semiconductor elements through a nozzle from above side faces of the stacked semiconductor elements, and curing the charged underfill agent.Type: GrantFiled: September 28, 2005Date of Patent: December 2, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 7435626Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.Type: GrantFiled: June 15, 2004Date of Patent: October 14, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Yasufumi Uchida, Yoshihiro Saeki
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Publication number: 20080237892Abstract: A semiconductor device having a first rectangular chip on which wires, electrode pads and chip mounting area are provided, a first dame formed on the first rectangular chip around the electrode pads and the chip mounting area so as to cover the wires and an under fill formed by filling liquid resin between a second rectangular chip mounted on the chip mounting area in a flip-chip manner and the first rectangular chip.Type: ApplicationFiled: March 11, 2008Publication date: October 2, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Yoshihiro Saeki
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Publication number: 20080237895Abstract: The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.Type: ApplicationFiled: March 6, 2008Publication date: October 2, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Yoshihiro Saeki
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Patent number: 7372137Abstract: A semiconductor device includes a lower substrate having wiring patterns formed of a plurality of wirings, semiconductor chips located above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chips in columnar form and substantially, and a resin board which substantially covers the entire upper surface of the intermediate member. A thermal expansion coefficient of the resin board and a thermal expansion coefficient of the lower substrate are made approximately identical to each other.Type: GrantFiled: August 9, 2006Date of Patent: May 13, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshihiro Saeki
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Publication number: 20080047345Abstract: An acceleration sensor chip package includes an acceleration sensor chip formed of a frame portion with an opening portion, a movable structure, a detection element, and an electrode pad. The movable structure has a beam portion and a movable portion supported on the beam portion to be movable. The acceleration sensor chip package further includes a re-wiring layer with a wiring portion having one end connected to the electrode pad; an outer terminal connected to the other end of the wiring portion; a first sealing portion for sealing the electrode pad and the re-wiring layer; and a substrate for sealing the opening portion of the frame portion.Type: ApplicationFiled: October 18, 2007Publication date: February 28, 2008Inventor: Yoshihiro Saeki
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Patent number: 7299696Abstract: An acceleration sensor chip package includes an acceleration sensor chip formed of a frame portion with an opening portion, a movable structure, a detection element, and an electrode pad. The movable structure has a beam portion and a movable portion supported on the beam portion to be movable. The acceleration sensor chip package further includes a re-wiring layer with a wiring portion having one end connected to the electrode pad; an outer terminal connected to the other end of the wiring portion; a first sealing portion for sealing the electrode pad and the re-wiring layer; and a substrate for sealing the opening portion of the frame portion.Type: GrantFiled: September 29, 2005Date of Patent: November 27, 2007Assignee: Oki Electric Industry Co., LtdInventor: Yoshihiro Saeki
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Publication number: 20070257374Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.Type: ApplicationFiled: November 3, 2006Publication date: November 8, 2007Applicant: Oki Electric Industry Co., Ltd.Inventor: Yoshihiro Saeki
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Publication number: 20070072345Abstract: A method of manufacturing a semiconductor device is disclosed, which includes at least the steps of preparing a laminated structure including a single chip or a plurality of chips, and dividing the laminated structure into a plurality of sub-laminated structures. A laminated structure comprised of a silicon substrate and a single chip or a plurality of chips laminated on the silicon substrate is formed. Then, the laminated structure is divided into a plurality of sub-laminated structures. Each of the sub-laminated structures includes a semiconductor device.Type: ApplicationFiled: September 14, 2006Publication date: March 29, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Yoshihiro SAEKI