Abstract: A jig is used for dicing a semiconductor device on which a plurality of chip regions are formed. The jig includes partitions that forms grids and a bottom wall the partitions are supported. When the semiconductor wafer is placed on the jig, the partitions support dicing regions of the semiconductor wafer such that at least one cavity is defined by the semiconductor wafer, the partitions, and the bottom wall. A negative pressure is created in the recesses by evacuating the air from the recesses. The semiconductor wafer is diced at the dicing regions into a plurality chips. The pressure in the recesses is returned to atmospheric pressure. Then, each of the chips is picked up from the jig.

Abstract: The present invention provides a semiconductor device which comprises a lower substrate having wiring patterns formed of a plurality of wirings, semiconductor chips located above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chips in columnar form and substantially, and a resin board which substantially covers the entire upper surface of the intermediate member. A thermal expansion coefficient of the resin board and a thermal expansion coefficient of the lower substrate are made approximately identical to each other.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: The present invention provides a semiconductor device comprising a lower substrate having at least one wiring pattern formed of a plurality of wirings, a semiconductor chip positioned above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chip in columnar form and substantially, and an upper plate which substantially covers a whole upper surface of the intermediate member. A thermal expansion coefficient of the upper plate and a thermal expansion coefficient of the lower substrate are set substantially identical.

Abstract: A method for forming a laminated structure in which four or more chips are laminated together includes at least a step of laminating a first chip sub-block comprised of a plurality of laminated chips together with a second chip sub-block comprised of a plurality of laminated chips.

Abstract: A method for manufacturing a semiconductor device formed by stacking a plurality of semiconductor elements on a substrate, comprises the steps of stacking the plurality of semiconductor elements on the substrate to form plural stages, placing the substrate substantially vertically and charging an underfill agent into spaces defined between the substrate and the corresponding semiconductor element and spaces defined among the stacked semiconductor elements through a nozzle from above side faces of the stacked semiconductor elements, and curing the charged underfill agent.

Abstract: An acceleration sensor chip package includes an acceleration sensor chip formed of a frame portion with an opening portion, a movable structure, a detection element, and an electrode pad. The movable structure has a beam portion and a movable portion supported on the beam portion to be movable. The acceleration sensor chip package further includes a re-wiring layer with a wiring portion having one end connected to the electrode pad; an outer terminal connected to the other end of the wiring portion; a first sealing portion for sealing the electrode pad and the re-wiring layer; and a substrate for sealing the opening portion of the frame portion.

Abstract: An electrical inspection method and apparatus for film carrier tapes for the electronic component mounting, and a computer-readable recording medium for inspecting a wiring pattern without causing a defective appearance by discharge breakdown even when the wiring pattern has protrusions between wires. The inspection method comprises applying a first voltage V1 between adjacent wires and measuring the current between the wires to detect the presence or absence of leakage current attributed to protrusions that extend from the respective wires and have an interval between the tips thereof within a predetermined range; and applying a second voltage V2 between adjacent wires of the wiring pattern found to be free of leakage current and measuring the current between the wires to detect the presence or absence of leakage current attributed to protrusions that extend from the respective wires and have an interval between the tips thereof which is larger than the predetermined range.

Abstract: A semiconductor device according to the present invention comprises, on a first semiconductor chip, a first circuit element region in which a first electrode group is arranged along an outer periphery of the first semiconductor chip in such a manner as to surround a second semiconductor chip, a second electrode group is arranged along the outer periphery of the first semiconductor chip in such a manner as to surround the first electrode group, and the first semiconductor chip is surrounded by the first electrode group, and a second circuit element region which surrounds the first electrode group and is surrounded by the second electrode group.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: Disposal and replacement of bonding pads is conducted easily and accurately. A semiconductor chip that includes bonding pads is fixed on a die pad. A relay chip is fixed on the semiconductor chip via an insulating material. The relay chip includes bonding pads that are interconnected via a wiring pattern, which includes a single-layer or multi-layer interconnection structure, and convert the disposition of the bonding pads of the semiconductor chip to a different direction. The bonding pads of the semiconductor chip are connected to the bonding pads of the relay chip via wires, and the bonding pads of the relay chip are connected to bonding pads of a lead frame via wires.

Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.

Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.

Abstract: A semiconductor device has a first chip fixed and connected to a substrate, wherein the first chip includes redistributions sealed with a sealing resin and for connecting between an integrated circuit formed on the surface of a semiconductor chip and ball pads, and solder bumps for connection to the substrate, which are respectively mounted on the ball pads.

Abstract: Disposal and replacement of bonding pads is conducted easily and accurately. A semiconductor chip that includes bonding pads is fixed on a die pad. A relay chip is fixed on the semiconductor chip via an insulating material. The relay chip includes bonding pads that are interconnected via a wiring pattern, which comprises a single-layer or multi-layer interconnection structure, and convert the disposition of the bonding pads of the semiconductor chip to a different direction. The bonding pads of the semiconductor chip are connected to the bonding pads of the relay chip via wires, and the bonding pads of the relay chip are connected to bonding pads of a lead frame via wires.

Abstract: A semiconductor device has a first chip (10A) fixed and connected to a substrate (30), wherein the first chip (10A) includes redistributions (14) sealed up with an sealing resin (16), for connecting between an integrated circuit formed on the surface of a semiconductor chip (11) and ball pads (15), and solder bumps (17) for connection to the substrate (30), which are respectively mounted on the ball pads (15).

Abstract: There are provided a semiconductor device construction having more degrees of design freedom of the semiconductor element than prior arts, and a method of manufacturing such device easily and at low cost. For this purpose, a rearrangement sheet is employed provided with an insulating sheet and conductive metallic patterns formed on this insulating sheet.