Patents by Inventor Yoshihiro Takemae

Yoshihiro Takemae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10318195
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 11, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Yoshihiro Takemae
  • Patent number: 10133498
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 20, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Yoshihiro Takemae
  • Publication number: 20180307423
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventor: Yoshihiro TAKEMAE
  • Publication number: 20160320999
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventor: Yoshihiro TAKEMAE
  • Patent number: 9418029
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 16, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Yoshihiro Takemae
  • Publication number: 20150154129
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: January 30, 2015
    Publication date: June 4, 2015
    Inventor: Yoshihiro TAKEMAE
  • Patent number: 8977832
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972686
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972688
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8972687
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8886897
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: November 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Patent number: 8878571
    Abstract: A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Yoshihiro Takemae
  • Patent number: 8836380
    Abstract: A semiconductor device, includes: a first field effect transistor having one terminal to which a first electrical potential is given; a second field effect transistor having one terminal to which a second electrical potential smaller than the first electrical potential is given; a controller that controls each electrical potential of each control terminal of the first field effect transistor and the second field effect transistor; a capacitor element having one end connected to the control terminal of the first field effect transistor, the capacitor element being charged by the control of the controller; and a load element connected between another terminal of the first field effect transistor and another terminal of the second field effect transistor.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Yoshihiro Takemae
  • Patent number: 8773176
    Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Transphorm Japan Inc.
    Inventors: Yasumori Miyazaki, Yoshihiro Takemae
  • Patent number: 8766711
    Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Yoshihiro Takemae
  • Publication number: 20140084966
    Abstract: A driver circuit includes an output terminal connected to a gate of a Schottky transistor, a reference transistor formed in the same manner as the Schottky transistor, a resistor connected between a first power source line and a gate of the reference transistor, a voltage generator configured to supply a second node with a voltage equal to or lower than a voltage at a first node between the resistor and the reference transistor, and a switching element configured to transmit the voltage at the second node to the output terminal in response to a signal inputted to an input terminal.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 27, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yoshihiro TAKEMAE
  • Patent number: 8683165
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshihiro Takemae
  • Publication number: 20130297890
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventor: Yoshihiro TAKEMAE
  • Publication number: 20130297860
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventor: Yoshihiro TAKEMAE
  • Publication number: 20130297862
    Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access. the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventor: Yoshihiro TAKEMAE