Patents by Inventor Yoshihiro Takemae
Yoshihiro Takemae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7388791Abstract: Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.Type: GrantFiled: October 19, 2006Date of Patent: June 17, 2008Assignee: Fujitsu LimitedInventors: Yoshiharu Kato, Yoshihiro Takemae, Toshio Ogawa, Tetsuhiko Endoh, Yoshinori Okajima
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Patent number: 7386659Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: GrantFiled: August 18, 2006Date of Patent: June 10, 2008Assignee: Fujitsu LimitedInventor: Yoshihiro Takemae
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Patent number: 7370141Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: GrantFiled: August 18, 2006Date of Patent: May 6, 2008Assignee: Fujitsu LimitedInventor: Yoshihiro Takemae
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Publication number: 20070230231Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.Type: ApplicationFiled: August 3, 2006Publication date: October 4, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070189100Abstract: A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data to a bus connected to a semiconductor memory MEM. For example, a microcontroller CNT in a system MSYS can use the bus during the data transfer since the bus is not used for the data transfer. As a result, it is possible to prevent the performance of the system MSYS from being deteriorated due to the data transfer.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070192664Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070189052Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070192527Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.Type: ApplicationFiled: May 31, 2006Publication date: August 16, 2007Inventors: Toshio Ogawa, Yoshihiro Takemae, Yoshinori Okajima, Tetsuhiko Endo, Yasuro Matsuzaki
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Publication number: 20070091989Abstract: Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.Type: ApplicationFiled: October 19, 2006Publication date: April 26, 2007Inventors: Yoshiharu Kato, Yoshihiro Takemae, Toshio Ogawa, Tetsuhiko Endoh, Yoshinori Okajima
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Publication number: 20070091678Abstract: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.Type: ApplicationFiled: October 19, 2006Publication date: April 26, 2007Inventors: Yoshiharu Kato, Yoshihiro Takemae, Toshio Ogawa, Tetsuhiko Endoh, Yoshinori Okajima
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Patent number: 7165159Abstract: A memory controller converts controller output signals output from a controller int memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: GrantFiled: October 20, 2003Date of Patent: January 16, 2007Assignee: Fujitsu LimitedInventor: Yoshihiro Takemae
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Publication number: 20060282608Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: ApplicationFiled: August 18, 2006Publication date: December 14, 2006Inventor: Yoshihiro Takemae
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Publication number: 20060282581Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: ApplicationFiled: August 18, 2006Publication date: December 14, 2006Inventor: Yoshihiro Takemae
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Publication number: 20060282582Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.Type: ApplicationFiled: August 18, 2006Publication date: December 14, 2006Inventor: Yoshihiro Takemae
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Patent number: 7042798Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.Type: GrantFiled: May 26, 2004Date of Patent: May 9, 2006Assignee: Fujitsu LimitedInventors: Yoshiharu Kato, Gen Tsukishiro, Yoshihiro Takemae
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Publication number: 20050242864Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.Type: ApplicationFiled: February 11, 2005Publication date: November 3, 2005Inventors: Kenichi Kawasaki, Yasuharu Sato, Terumasa Kitahara, Masao Nakano, Masao Taguchi, Yoshihiro Takemae, Yasurou Matsuzaki, Koichi Nishimura, Yoshinori Okajima, Naoharu Shinozaki, Hiroko Douchi
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Publication number: 20050157585Abstract: It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.Type: ApplicationFiled: May 26, 2004Publication date: July 21, 2005Inventors: Yoshiharu Kato, Gen Tsukishiro, Yoshihiro Takemae
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Patent number: 6744300Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.Type: GrantFiled: October 23, 2002Date of Patent: June 1, 2004Assignee: Fujitsu LimitedInventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
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Patent number: 6737893Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.Type: GrantFiled: October 23, 2002Date of Patent: May 18, 2004Assignee: Fujitsu LimitedInventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
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Patent number: 6720804Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.Type: GrantFiled: October 23, 2002Date of Patent: April 13, 2004Assignee: Fujitsu LimitedInventors: Masao Taguchi, Yoshihiro Takemae