Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A semiconductor memory device includes a memory part which stores data, a decoder which decodes a command externally supplied to the semiconductor memory device, and a precharge protection circuit which dynamically determines, based on the command decoded by the decoder, a period necessary to precharge a predetermined circuit part of the semiconductor memory device, so that a precharge operation on the predetermined circuit part can be protected.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs.

Abstract: A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A data transfer apparatus is disclosed which has a first, a second, and a third pipeline processing circuits disposed in cascade connection. The first and the second pipeline processing circuits are each provided with an arbitrary signal processing circuit, a switch element for controlling the introduction of data into the signal processing circuit, and a switch control circuit for turning on the switch element on detecting completion of the transfer of data from the signal processing circuit to a pipeline processing circuit in the subsequent stage. The third pipeline processing circuit is provided with an output circuit and a switch element for introducing data transferred from the second pipeline processing circuit into the output circuit as synchronized with an external clock signal.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A semiconductor memory has a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a power source unit, and a plurality of sense amplifiers. The memory cells are formed at intersection portions of the bit lines and the word lines, and each of the memory cells includes a transistor and a capacitor. The power source unit is connected to the capacitors of the memory cells. Each of the sense amplifiers, which is connected to a corresponding one of the bit lines and the power source, is used to amplify a voltage between a potential of the corresponding bit line. This memory realizes high integration, large capacity, and low power consumption.

Abstract: The present invention relates to a word driver circuit provided in a memory circuit. The word driver circuit comprises a P channel and an N channel transistor having a gate electrode commonly connected and one source or drain electrode commonly connected. The N channeltransistor has another source or drain electrode connected to a ground. A word line is connected to the commonly connected source or drain electrode of the transistors. A first selection signal, generated by decoding a first group of address signals, whose potential is either a first potential by which the N channel transistor is rendered conductive or a second potential lower than the first power supply is supplied to the gate electrodes. And a second selection signal, generated by decoding a second group of address signals, whose potential is either a third potential of the selected word line or a fourth potential equal or lower than the first power supply is supplied to another source or drain of the P transistor.

Abstract: A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Abstract: A memory and a method for reading out of memory including a register for holding one row of data of a memory cell array, a plurality of first switching transistors for switching ON/OFF between a plurality of bit lines and the corresponding bits in the register, a plurality of second switching transistors for switching ON/OFF between the bit lines and a pair of data bus lines and a plurality of third switching transistors for switching ON/OFF between the data bus lines and the bits in the register. In random access of memory cells, selection and control is performed for the plurality of second switching transistors with an output of a column decoder. In sequential reading out of the register, one row data of the memory cells selected by a row decoder are written in the register by controlling the plurality of first switching transistors and with an output of the column decoder, sequential selection and control of the plurality of third switching transistors is performed.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.

Abstract: A semiconductor memory device includes a plurality of banks each having a memory cell array and sense amplifiers, a data input/output circuit and an address circuit. A first part of the device receives control signals from an outside of the semiconductor memory device and generates a refresh signal therefrom. A second part generates bank select signals in response to the refresh signal, the bank select signals being used to select the plurality of banks. A third part receives the bank select signals and generating latch enable signals therefrom, the latch enable signals driving the sense amplifiers provided in the plurality of banks. A refresh operation is carried out by activating the sense amplifiers by using the latch enable signals.

Abstract: A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.

Abstract: A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.