Patents by Inventor Yoshihisa Abe

Yoshihisa Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10802031
    Abstract: An object of the present invention is to provide a biomarker capable of determining the onset risk or the stage of diabetic nephropathy (early-stage diabetic nephropathy in particular). Diabetic nephropathy is determined by measuring or quantitatively determining a concentration of phenyl sulfate or a salt thereof (a phenyl sulfate) contained in a biological sample, preferably plasma or urine, collected from a test subject to detect a phenyl sulfate. The present invention exhibits excellent effects particularly for stage determination for stage 1 (pre-nephropathy stage) to stage 3 (overt nephropathy stage), or for determination of onset risk of diabetic nephropathy (diabetic nephropathy at pre-nephropathy stage).
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 13, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takaaki Abe, Susumu Ogawa, Yoshihisa Tomioka
  • Publication number: 20200194545
    Abstract: A nitride semiconductor substrate can effectively reduce leakage current in the vertical direction. The nitride semiconductor substrate comprises a buffer layer and an operation layer, both of which are made of nitride semiconductor, deposited on a silicon single crystal substrate, wherein the buffer layer comprises a single-layered first initial layer in contact with the silicon single crystal layer, and a single-layered second initial layer in contact with the first initial layer, the first initial layer is made of AlN, the second initial layer is made of AlzGa1-zN (0.12?z?0.65), and in an X-Y graph where the X-axis denotes z×100 and the Y-axis denotes carbon concentration in the second initial layer, X ranges from 12 to 65 and Y is within a range between Y=1E+17×exp(?0.05×X) and Y=1E+21×exp(?0.05×X).
    Type: Application
    Filed: October 9, 2019
    Publication date: June 18, 2020
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Jun KOMIYAMA
  • Publication number: 20200194580
    Abstract: Provided is a nitride semiconductor structure capable of preventing deterioration of transistor characteristics caused by diffusion of a P-type conductive element by using an extremely simple configuration, instead of introducing a diffusion suppression layer. A nitride semiconductor substrate comprises at least a layered structure made of group 13 nitride semiconductors, wherein a first layer, a second layer having a wider band gap than the first layer, and a third layer containing a P-type conductive impurity at a concentration of 5E+18 atoms/cc or more are stacked in this order in the layered structure, and a maximum concentration of P-type conductive impurity in the first layer is 10% or less of the concentration of P-type conductive impurity in the third layer.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 18, 2020
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Jun KOMIYAMA
  • Patent number: 10593790
    Abstract: A structure for increasing the concentration of two-dimensional electron gas without lowering mobility is provided. That is, a nitride semiconductor substrate is provided which includes a first layer, a second layer, and a third layer. The first layer has a composition of Ina1Alb1Gac1N (0?a1?1, 0?b1?1, 0?c1?1, a1+b1+c1=1). The second layer is formed on the first layer. The second layer has a composition of Ina2Alb2Gac2N (0?a2?1, 0?b2?1, 0?c2?1, a2+b2+c2=1) and has a band gap different from that of the first layer. The third layer is formed on the second layer and has a composition of AjB1-jN (A is a group 13 element, B is a group 13 element or a group 14 element, A?B, 0<j<1).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 17, 2020
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Masashi Kobata, Shintaro Miyamoto
  • Patent number: 10559679
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a channel layer, a spacer layer, and an electron supply layer that are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1-aN (0<a<0.5). The electron supply layer is AlxlnyGa1-x-yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 11, 2020
    Assignee: COORSTEK KK
    Inventors: Hiroshi Oishi, Noriko Omori, Yoshihisa Abe
  • Patent number: 10522386
    Abstract: Provided are a susceptor that, in forming a thin film on a wafer, can reduce impurities or the like adhering to the wafer and a method for manufacturing the same. A susceptor includes a base material (10) with a recess (11), a tantalum carbide layer (22) formed directly on a bottom surface (11a) and a side surface (11b) of the recess (11), and a silicon carbide layer (20) formed on a surface of the base material (10) except for the recess (11).
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: December 31, 2019
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Masato Shinohara, Yoshihisa Abe, Satoru Nogami
  • Publication number: 20190301472
    Abstract: A counter-rotating fan includes a first fan including a first impeller including first blades radially arranged around a predetermined center axis, a first motor that rotates the first impeller around the center axis, and a first case surrounding an outer circumference of the first impeller, and a second fan including a second impeller including second blades radially arranged around the center axis, a second motor that rotates the second impeller around the center axis, and a second case surrounding an outer circumference of the second impeller. The first blades include a front edge located foremost in a rotation direction and a rear edge located rearmost in the rotation direction. A radially outermost end of the rear edge is located closer to the second fan than a radially innermost end.
    Type: Application
    Filed: February 12, 2019
    Publication date: October 3, 2019
    Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
  • Publication number: 20190301473
    Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.
    Type: Application
    Filed: March 15, 2019
    Publication date: October 3, 2019
    Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
  • Publication number: 20190158756
    Abstract: An optical measuring device comprises: a lens to form an image with reflected light from a measuring object; an image sensor to receive the reflected light that has passed through the lens and generate an image representing the measuring object; a driver to drive a drive object, the drive object being at least one of the lens and the image sensor; and a controller to control the optical measuring device. The controller acquires, from the image sensor, a plurality of images generated by the image sensor successively imaging the measuring object while the driver is driving the drive object in accordance with a predetermined driving pattern, and outputs the plurality of images.
    Type: Application
    Filed: April 5, 2017
    Publication date: May 23, 2019
    Inventors: Koji YAMAMOTO, Satoshi YOKOTA, Norimasa KUBOTA, Yoshihisa ABE, Yuta YAMANOI, Masaaki CHIGASAKI, Osamu TOYAMA
  • Publication number: 20190154508
    Abstract: Colorimeter having first and second illumination units disposed symmetrically to a reference line in a prescribed plane, first and second light-receiving parts disposed symmetrically to the reference line in the prescribed plane, a calculation unit for determining color information about a measurement object, and an opposing wall that opposes the measurement object when it is measured. The opposing wall has an abutting part that abuts the measurement object when it is measured. The abutting part has a pair of first abutting parts disposed on two sides of a measurement opening to flank the measurement opening; and a pair of second abutting parts disposed on an orthogonal line orthogonal to a first-abutting-part connection line that connects the pair of first abutting parts to each other, the pair of second abutting parts being disposed on two sides of the first-abutting-part connection line to flank the first-abutting-part connection line.
    Type: Application
    Filed: July 5, 2017
    Publication date: May 23, 2019
    Inventors: Hiroki AOMATSU, Shinichi IIDA, Wataru YAMAGUCHI, Yoshitaka TERAOKA, Yoshihisa ABE
  • Publication number: 20190074369
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a spacer structure capable of obtaining characteristics unprecedented in the prior art. In the nitride semiconductor epitaxial substrate of the present invention, a channel layer, a spacer layer, and an electron supply layer are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1?aN (0<a<0.5). The electron supply layer is AlxInyGa1?x?yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less. Thus, adverse effects due to the existence of a conventional spacer layer are suitably suppressed.
    Type: Application
    Filed: August 17, 2018
    Publication date: March 7, 2019
    Applicant: CoorsTek KK
    Inventors: Hiroshi OISHI, Noriko OMORI, Yoshihisa ABE
  • Patent number: 10068858
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 4, 2018
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Noriko Omori, Hiroshi Oishi, Jun Komiyama
  • Publication number: 20180240903
    Abstract: A structure for increasing the concentration of two-dimensional electron gas without lowering mobility is provided. That is, a nitride semiconductor substrate is provided which includes a first layer, a second layer, and a third layer. The first layer has a composition of Ina1Alb1Gac1N (0?a1?1, 0?b1?1, 0?c1?1, a1+b1+c1=1). The second layer is formed on the first layer. The second layer has a composition of Ina2Alb2Gac2N (0?a2?1, 0?b2?1, 0?c2?1, a2+b2+c2=1) and has a band gap different from that of the first layer. The third layer is formed on the second layer and has a composition of AjB1-jN (A is a group 13 element, B is a group 13 element or a group 14 element, A?B, 0<j<1).
    Type: Application
    Filed: February 20, 2018
    Publication date: August 23, 2018
    Applicant: CoorsTek KK
    Inventors: Yoshihisa ABE, Masashi KOBATA, Shintaro MIYAMOTO
  • Publication number: 20180151714
    Abstract: Provided is a nitride semiconductor substrate which improves electron mobility and reduce a series resistance component of a transistor. In the nitride semiconductor substrate, an electron transit layer, an intermediate layer, and an electron supply layer are laminated in this order. The electron transit layer includes a nitride semiconductor of a first group 13 element. The intermediate layer and the electron supply layer each include a nitride semiconductor of the first group 13 element and a second group 13 element. The nitride semiconductor substrate has a profile in which an atomic ratio of the second group 13 element to a total of the first group 13 element and the second group 13 element increases in the thickness direction of the intermediate layer from an interface between the electron transit layer and the intermediate layer, and the atomic ratio decreases after a maximum peak value is obtained in the intermediate layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 31, 2018
    Applicant: CoorsTek KK
    Inventors: Noriko OMORI, Hiroshi OISHI, Yoshihisa ABE, Jun KOMIYAMA
  • Patent number: 9976905
    Abstract: Since both gloss and a reflection characteristic are measured by one surface characteristic measurement device, a gloss measurement target area and a reflection characteristic measurement target area are appropriately set. A gloss measurement instrument and a color measurement instrument are integrated with a gloss colorimeter. The gloss measurement instrument illuminates an illumination target face by illumination light, receives reflected light generated by a regular reflection of the illumination light on the illumination target face, and outputs a measurement result for the reflected light. A size of the gloss measurement target area can be changed. The color measurement instrument illuminates the illumination target face by annular illumination light, receives reflected light generated by a reflection of the annular illumination light on the illumination target face, and outputs a measurement result for the reflected light. A size of the reflection characteristic measurement target area can be changed.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 22, 2018
    Assignee: Konica Minolta, Inc.
    Inventors: Yosuke Takebe, Yoshihisa Abe
  • Patent number: 9885668
    Abstract: A surface inspection device includes an opening defining an aperture plane, one or more optical transceivers, and a processor. Each optical transceiver includes a light emitter and a light receiver that are arranged in different directions with respect to the aperture plane when viewed from above a virtual normal line of the aperture plane. The processor acquires detection values from the optical transceivers and calculates an evaluation value of a degree of variation in the detection values.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: February 6, 2018
    Assignee: Konica Minolta, Inc.
    Inventors: Takafumi Komatsu, Yoshihisa Abe, Wataru Yamaguchi, Yosuke Takebe
  • Publication number: 20170261439
    Abstract: A surface inspection device includes an opening defining an aperture plane, one or more optical transceivers, and a processor. Each optical transceiver includes a light emitter and a light receiver that are arranged in different directions with respect to the aperture plane when viewed from above a virtual normal line of the aperture plane. The processor acquires detection values from the optical transceivers and calculates an evaluation value of a degree of variation in the detection values.
    Type: Application
    Filed: July 21, 2015
    Publication date: September 14, 2017
    Applicant: Konica Minolta, Inc.
    Inventors: Takafumi Komatsu, Yoshihisa Abe, Wataru Yamaguchi, Yosuke Takebe
  • Patent number: 9748344
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 29, 2017
    Assignee: COORSTEK KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Publication number: 20170199079
    Abstract: Since both gloss and a reflection characteristic are measured by one surface characteristic measurement device, a gloss measurement target area and a reflection characteristic measurement target area are appropriately set. A gloss measurement instrument and a color measurement instrument are integrated with a gloss colorimeter. The gloss measurement instrument illuminates an illumination target face by illumination light, receives reflected light generated by a regular reflection of the illumination light on the illumination target face, and outputs a measurement result for the reflected light. A size of the gloss measurement target area can be changed. The color measurement instrument illuminates the illumination target face by annular illumination light, receives reflected light generated by a reflection of the annular illumination light on the illumination target face, and outputs a measurement result for the reflected light. A size of the reflection characteristic, measurement target area can be changed.
    Type: Application
    Filed: April 20, 2015
    Publication date: July 13, 2017
    Applicant: Konica Minolta, Inc.
    Inventors: Yosuke Takebe, Yoshihisa Abe
  • Publication number: 20170162425
    Abstract: Provided are a susceptor that, in forming a thin film on a wafer, can reduce impurities or the like adhering to the wafer and a method for manufacturing the same. A susceptor includes a base material (10) with a recess (11), a tantalum carbide layer (22) formed directly on a bottom surface (11a) and a side surface (11b) of the recess (11), and a silicon carbide layer (20) formed on a surface of the base material (10) except for the recess (11).
    Type: Application
    Filed: June 1, 2015
    Publication date: June 8, 2017
    Applicant: TOYO TANSO CO., LTD.
    Inventors: Masato Shinohara, Yoshihisa Abe, Satoru Nogami