Patents by Inventor Yoshihito Kobayashi

Yoshihito Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100147088
    Abstract: An electronic device test apparatus used for bringing the ICs into electrical contact with contact parts of the test head in the state where the ICs are held on a test tray and running tests on the electrical characteristics of ICs, the electronic device test apparatus including an inversion system for rotating the test tray which holds a plurality of ICs in a direction dropping ICs which are insufficiently held at least once before testing.
    Type: Application
    Filed: January 17, 2006
    Publication date: June 17, 2010
    Applicant: ADVANTEST CORPORATION
    Inventors: Akihiko Ito, Koya Karino, Yoshihito Kobayashi
  • Publication number: 20100148793
    Abstract: An electronic device test apparatus includes a plurality of testers on which are mounted test heads that are connected to test outputters for outputting test signals to the electronic devices and for receiving response signals from the electronic devices. A loading transporter is provided at a frontmost stage of the testers that transports the electronic devices from a previous process conveyance medium to a test tray before loading the electronic devices into the testers. An unloading transporter is provided at a rearmost stage of the testers that unloads the electronic devices from the test tray to a later process conveyance medium corresponding to the response signals. A transporter is provided between the testers that transports the test tray from a previous process tester to a later process tester. The transporter includes a buffer that holds test trays to absorb a waiting time due to differences in processing capacities between test trays.
    Type: Application
    Filed: September 24, 2009
    Publication date: June 17, 2010
    Applicant: ADVANTEST CORPORATION
    Inventors: Akihiko ITO, Kazuyuki YAMASHITA, Yoshihito KOBAYASHI
  • Patent number: 7612575
    Abstract: An apparatus having a plurality of test units (520), a loading transport unit (510) transporting a plurality of electronic devices from a customer tray (4C) to a test tray (4T) before being loaded in a test unit, and a classifying transport unit (530) transporting a plurality of electronic devices from a test tray while classifying them to customer trays in accordance with test results, the loading transport unit being provided at least at a frontmost stage of a plurality of test units, the classifying transport unit being provided at least at a rearmost stage of the plurality of test units, the test tray being successively conveyed from the frontmost stage to the rearmost stage of the plurality of test units in the state carrying electronic devices and returned from the rearmost stage test unit to the frontmost stage test unit.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: November 3, 2009
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Kazuyuki Yamashita, Yoshihito Kobayashi
  • Publication number: 20080038098
    Abstract: An apparatus having a plurality of test units (520), a loading transport unit (510) transporting a plurality of electronic devices from a customer tray (4C) to a test tray (4T) before being loaded in a test unit, and a classifying transport unit (530) transporting a plurality of electronic devices from a test tray while classifying them to customer trays in accordance with test results, the loading transport unit being provided at least at a frontmost stage of a plurality of test units, the classifying transport unit being provided at least at a rearmost stage of the plurality of test units, the test tray being successively conveyed from the frontmost stage to the rearmost stage of the plurality of test units in the state carrying electronic devices and returned from the rearmost stage test unit to the frontmost stage test unit.
    Type: Application
    Filed: July 25, 2005
    Publication date: February 14, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: Akihiko Ito, Kazuyuki Yamashita, Yoshihito Kobayashi
  • Patent number: 6856128
    Abstract: An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: February 15, 2005
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi, Yoshiyuki Masuo, Tsuyoshi Yamashita
  • Patent number: 6728652
    Abstract: A method of judging whether an electronic component is good or defective in accordance with a response output signal by inputting a test signal to the IC to be tested, wherein a common test signal is input to respective electronic devices A1 and A2 of a group of electronic devices composed of a plurality of electronic devices, and in accordance with a response signal thereof, the group of electronic devices as a whole subjected to the test is judged to be good or defective. In the second test, each of the DUTs A1 and A2 of the group of electronic devices judged to be defective is input a mutually independent test signal, and in accordance with the response signal thereof, it is judged whether each of the electronic devices A1 and A2 subjected to the test is good or defective.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: April 27, 2004
    Assignee: Advantest Corporation
    Inventor: Yoshihito Kobayashi
  • Patent number: 6459259
    Abstract: An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: October 1, 2002
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi, Yoshiyuki Masuo, Tsuyoshi Yamashita
  • Publication number: 20020135356
    Abstract: An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
    Type: Application
    Filed: February 26, 1999
    Publication date: September 26, 2002
    Inventors: AKIHIKO ITO, YOSHIHITO KOBAYASHI, YOSHIYUKI MASUO, TSUYOSHI YAMASHITA
  • Patent number: 6445203
    Abstract: An electric device testing apparatus comprises a connection terminal to which an IC chip to be tested is removably connected, a pusher for pushing the IC chip in the direction of the connection terminal in order to connect the IC chip to the connection terminal, and temperature adjusted air supply for blowing a temperature adjusted air to around the IC chip during a test on the IC chip via a through hole formed on the pushed.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: September 3, 2002
    Assignee: Advantest Corporation
    Inventors: Tsuyoshi Yamashita, Yoshihito Kobayashi, Toshiyuki Kiyokawa, Hiroto Nakamura, Noriyuki Igarashi, Kenichi Shimada
  • Patent number: 6437593
    Abstract: An electric device testing apparatus for carrying out a test by pushing a terminal of an IC against a contact portion of a test head, comprising a temperature calculation means for calculating an actual temperature of the IC based on a signal from a temperature sensing element provided on the IC.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: August 20, 2002
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi
  • Patent number: 6433294
    Abstract: A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: August 13, 2002
    Assignee: Advantest Corporation
    Inventors: Shin Nemoto, Yoshihito Kobayashi, Hiroo Nakamura, Takeshi Onishi, Hiroki Ikeda
  • Patent number: 6406246
    Abstract: A device handler having a device holder 200 in which are provided a plurality of feed stockers 201 and/or storing stockers 202, provided with an IC card reader 260 able to read and/or write identification data of an IC card 270 provided at each of the feed stockers 201 and/or storing stockers 202 and a movement mechanism 205 for moving the IC card reader 260 inside the device holder 200. The movement mechanism 205 is a tray movement arm. It is possible to simplify the configuration of the handler and lower the cost while enabling extremely easy reading and/or writing of identification data provided at the feed stocker and/or storing stocker.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 18, 2002
    Assignee: Advantest Corporation
    Inventors: Akihiko Itoh, Yoshihito Kobayashi
  • Patent number: 6384593
    Abstract: A semiconductor device testing apparatus having a reduced transverse width and compact in size is provided. Adjacent to a constant temperature chamber containing therein a vertical transport means is located a test chamber which is in turn adjoined by a temperature-stress removing chamber likewise containing therein a vertical transport means, so that the constant temperature chamber and the test chamber are arranged transversely in a line, while the temperature-stress removing chamber is located in front of the test chamber when viewed in front view of the apparatus. Further, a loader section is located in front of the constant temperature chamber, and an unloader section is located above the temperature-stress removing chamber. With this arrangement, the transverse width of the testing apparatus may be reduced to about two test tray lengths.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: May 7, 2002
    Assignee: Advantest Corporation
    Inventors: Yoshihito Kobayashi, Tsuyoshi Yamashita, Hiroto Nakamura, Shin Nemoto, Yoshiyuki Masuo, Akihiko Ito
  • Patent number: 6384360
    Abstract: A pad 1051, air cylinder 1052, cylinder control valve 1053, vacuum generator 1054, feed valve 1055, break valve 1056, and pressure sensor 1057 are assembled together to form an IC pickup 105d.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: May 7, 2002
    Assignee: Advantest Corporation
    Inventors: Yoshiyuki Masuo, Yoshihito Kobayashi
  • Publication number: 20020036161
    Abstract: A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means.
    Type: Application
    Filed: December 4, 2001
    Publication date: March 28, 2002
    Applicant: ADVANTEST CORPORATION
    Inventors: Shin Nemoto, Yoshihito Kobayashi, Hiroto Nakamura, Takeshi Onishi, Hiroki Ikeda
  • Publication number: 20020011836
    Abstract: An IC tester which is capable of reducing the time required before completion of testing on all of ICs to be tested is provided. The depth (length in the Y-axis direction) of the constant temperature chamber 4 and the exit chamber 5 is expanded by a dimension corresponding approximately to one transverse width (length of the minor edge) of the rectangular test tray 3, and two generally parallel test tray transport paths or alternatively a widened test tray transport path broad enough to transport two test trays simultaneously with the two test trays juxtaposed in a direction transverse to the widened test tray transport path are provided in the section of test tray transport path extending from the soak chamber 41 in the constant temperature chamber 4 through the testing section 42 in the constant temperature chamber 4 to the exit chamber 5 so that two test trays may be simultaneously transported along the two test tray transport paths or the widened test tray transport path.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 31, 2002
    Inventors: Akihiko Ito, Yoshihito Kobayashi, Yoshiyuki Masuo, Tsuyoshi Yamashita
  • Patent number: 6320398
    Abstract: A semiconductor device testing apparatus is provided which allows for eliminating the need to replace IC sockets even if the type of IC package is changed. A device receiving carrier 100 accommodating the IC to be tested has its bottom open. A fine conductive wire-embedded member 110 is mounted to the open bottom of the device receiving carrier. The wire-embedded member comprises a resilient rubber plate 111 and a number of fine conductive wires 112 embedded in the rubber plate, the fine conductive wires being electrically insulated from each other and extending through the thickness of the rubber plate with the opposite ends exposed at the opposed surfaces of the rubber plate. The IC to be tested is rested on the wire-embedded member. A board 70 is mounted to the test head, the board having gold pads 72 formed in a manner electrically insulated from each other in the surface thereof at at least the positions opposing the terminals of the IC to be tested placed on the top surface of the wire-embedded member.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: November 20, 2001
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi
  • Patent number: 6104183
    Abstract: A semiconductor device testing apparatus having a reduced transverse width and compact in size is provided. Adjacent to a constant temperature chamber 101 containing therein a vertical transport means is located a test chamber 102 which is in turn adjoined by a temperature-stress removing chamber 103 likewise containing therein a vertical transport means, so that the constant temperature chamber 101, the test chamber 102 and the temperature-stress removing chamber 103 are arranged transversely in a line. Further, a loader section 300 is located in front of the constant temperature chamber, and an unloader section 400 is located in front of the test chamber and the temperature-stress removing chamber. With this arrangement, the transverse width of the testing apparatus may be reduced to about three test tray lengths.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: August 15, 2000
    Assignee: Advantest Corporation
    Inventors: Yoshihito Kobayashi, Tsuyoshi Yamashita, Hiroto Nakamura, Shin Nemoto, Yoshiyuki Masuo, Akihiko Ito
  • Patent number: 6075216
    Abstract: An IC device transfer method for IC handler accommodates both a tray and a rod-shaped magazine. The tray installs a plurality of IC devices which transport in horizontal directions in the IC handler. The rod-shaped magazine installs a plurality of IC devices which transport in vertical directions in the IC handler. A device reinspection method in the IC test handler reinspects the IC devices stored in the tray or magazine without human intervention, sorts in accordance with the test results, and stores in either the rod-shaped magazine or the tray. For this purpose, a tray supply section transfers a user tray to a test tray, whereas a magazine supply section and a pick carrier section transfer a rod-shaped magazine to the test tray. An inspection setting sets the number of reinspection, the classification of inspection results, and the storage tray/magazine. The IC devices are loaded from the magazine and the user tray to the test tray and are tested.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: June 13, 2000
    Assignee: Advantest Corp.
    Inventors: Hiroto Nakamura, Yoshihito Kobayashi, Katsuhiko Suzuki
  • Patent number: D431580
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: October 3, 2000
    Assignee: Advantest Corporation
    Inventors: Akihiko Ito, Yoshihito Kobayashi