Patents by Inventor Yoshiki Endo

Yoshiki Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160108771
    Abstract: When a lock demand of a camshaft phase occurs, a control mode of a hydraulic control valve s switched to a locking mode after an actual camshaft phase is controlled to a lock phase, and a lock pin (an inner pin and an outer pin) is moved to a lock position. Thus, the camshaft phase is locked at the lock phase, and a timing advance chamber and a timing retard chamber are made a state of communicating with each other through a back space. In this state, a locking time filling control is executed. In the locking time filling control, the control mode of a hydraulic control valve is switched to a filling mode, the hydraulic oil is supplied to a timing advance chamber, both of the timing advance chamber and the timing retard chamber are filled with the hydraulic oil, the back space is filled with the hydraulic oil, and thereafter the control mode of the hydraulic control valve is returned to the locking mode.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 21, 2016
    Inventors: Shuhei OE, Shota TODA, Yoshiki ENDO, Yuu YOKOYAMA, Toshiki FUJIYOSHI
  • Patent number: 9175583
    Abstract: When a start-up failure occurs wherein an internal combustion engine equipped with a variable valve device does not transition to complete combustion before a first prescribed period ? elapses from the start of cranking in conjunction with fuel injection, a control unit for the internal combustion engine executes a start-up failure process addressing a state wherein the valve timing is different from a specific timing.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: November 3, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toshio Imamura, Yoshiaki Miyazato, Yuu Yokoyama, Masaki Numakura, Yoshiki Endo
  • Patent number: 9006881
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device, including an insulating substrate, at least one semiconductor chip provided above the insulating substrate, a wiring terminal including a connection portion electrically connected to the semiconductor chip, a surrounding frame surrounding the semiconductor chip and the connection portion, an embedded material provided in the surrounding frame covering the semiconductor chip and the connection portion, and a pressing unit provided on a surface of the embedded material.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Fukuyoshi, Junichi Nakao, Yoshiki Endo, Eitaro Miyake
  • Publication number: 20140284786
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device, including an insulating substrate, at least one semiconductor chip provided above the insulating substrate, a wiring terminal including a connection portion electrically connected to the semiconductor chip, a surrounding frame surrounding the semiconductor chip and the connection portion, an embedded material provided in the surrounding frame covering the semiconductor chip and the connection portion, and a pressing unit provided on a surface of the embedded material.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Fukuyoshi, Junichi Nakao, Yoshiki Endo, Eitaro Miyake
  • Publication number: 20130291835
    Abstract: When a start-up failure occurs wherein an internal combustion engine equipped with a variable valve device does not transition to complete combustion before a first prescribed period ? elapses from the start of cranking in conjunction with fuel injection, a control unit for the internal combustion engine executes a start-up failure process addressing a state wherein the valve timing is different from a specific timing.
    Type: Application
    Filed: January 20, 2011
    Publication date: November 7, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toshio Imamura, Yoshiaki Miyazato, Yuu Yokoyama, Masaki Numakura, Yoshiki Endo
  • Patent number: 8554455
    Abstract: An IIS system that performs control related to intermittent stopping of engine operation by idling stop control is applied to an internal combustion engine including a VVT mechanism that makes the valve timing of an engine valve variable and has an intermediate lock mechanism that mechanically locks the valve timing at an intermediate lock position between a most retarded position and a most advanced position. The IIS system is configured to inhibit the engine operation from being intermittently stopped at the occurrence of a failure of the VVT mechanism to avoid the internal combustion engine from being prevented from being restarted after the intermittent stop depending on the occurrence of the failure of the VVT mechanism.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 8, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yoshiaki Miyazato, Toshio Imamura, Yuu Yokoyama, Satoshi Yoshi, Yoshiki Endo, Yuu Ueda, Hiroyuki Ishii
  • Publication number: 20130152887
    Abstract: An IIS system that performs control related to intermittent stopping of engine operation by idling stop control is applied to an internal combustion engine including a VVT mechanism that makes the valve timing of an engine valve variable and has an intermediate lock mechanism that mechanically locks the valve timing at an intermediate lock position between a most retarded position and a most advanced position. The IIS system is configured to inhibit the engine operation from being intermittently stopped at the occurrence of a failure of the VVT mechanism to avoid the internal combustion engine from being prevented from being restarted after the intermittent stop depending on the occurrence of the failure of the VVT mechanism.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 20, 2013
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yoshiaki Miyazato, Toshio Imamura, Yuu Yokoyama, Satoshi Yoshi, Yoshiki Endo, Yuu Ueda, Hiroyuki Ishii
  • Patent number: 7633153
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: December 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Patent number: 7514783
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: April 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Patent number: 7329903
    Abstract: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to the light emitted from the light emitting layer. The substrate defines a top surface supporting the light emitting layer thereon; a bottom surface opposed to the top surface and side surfaces connecting the top surface and the bottom surface. Each of the side surfaces is composed of first side surface extending from the top surface toward the bottom surface, second side surface extending from the first side surface toward the bottom surface, and third side surface extending from the second side surface toward the bottom surface.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: February 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Takafumi Nakamura, Kuniaki Konno, Yasuhiko Akaike, Yoshiki Endo, Katsufumi Kondo
  • Publication number: 20070257708
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20070257376
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20060151798
    Abstract: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to the light emitted from the light emitting layer. The substrate defines a top surface supporting the light emitting layer thereon; a bottom surface opposed to the top surface and side surfaces connecting the top surface and the bottom surface. Each of the side surfaces is composed of first side surface extending from the top surface toward the bottom surface, second side surface extending from the first side surface toward the bottom surface, and third side surface extending from the second side surface toward the bottom surface.
    Type: Application
    Filed: March 9, 2006
    Publication date: July 13, 2006
    Inventors: Koichi Nitta, Takafumi Nakamura, Kuniaki Konno, Yasuhiko Akaike, Yoshiki Endo, Katsufumi Kondo
  • Publication number: 20060145171
    Abstract: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to the light emitted from the light emitting layer. The substrate defines a top surface supporting the light emitting layer thereon; a bottom surface opposed to the top surface and side surfaces connecting the top surface and the bottom surface. Each of the side surfaces is composed of first side surface extending from the top surface toward the bottom surface, second side surface extending from the first side surface toward the bottom surface, and third side surface extending from the second side surface toward the bottom surface.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 6, 2006
    Inventors: Koichi Nitta, Takafumi Nakamura, Kuniaki Konno, Yasuhiko Akaike, Yoshiki Endo, Katsufumi Kondo
  • Patent number: 7038245
    Abstract: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to the light emitted from the light emitting layer. The substrate defines a top surface supporting the light emitting layer thereon; a bottom surface opposed to the top surface and side surfaces connecting the top surface and the bottom surface. Each of the side surfaces is composed of first side surface extending from the top surface toward the bottom surface, second side surface extending from the first side surface toward the bottom surface, and third side surface extending from the second side surface toward the bottom surface.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nitta, Takafumi Nakamura, Kuniaki Konno, Yasuhiko Akaike, Yoshiki Endo, Katsufumi Kondo
  • Publication number: 20060055432
    Abstract: A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 16, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Masako Ooishi, Tatsuya Yamada, Osamu Usuda, Yoshiki Endo, Taiki Miura, Masaki Toyoshima, Ichiro Omura, Akio Nakagawa, Kenichi Matsushita, Yusuke Kawaguchi, Haruki Arai, Hiroshi Takei, Tomohiro Kawano, Noriaki Yoshikawa, Morio Takahashi, Yasuhito Saito, Masahiro Urase
  • Publication number: 20030197191
    Abstract: For the purpose of enhancing the light extracting efficiency, improving the production yield and elongating the lifetime of a semiconductor light emitting element or a semiconductor light emitting device using the element, a semiconductor light emitting element comprises: a light emitting layer that emits light; and a substrate transparent to the light emitted from the light emitting layer. The substrate defines a top surface supporting the light emitting layer thereon; a bottom surface opposed to the top surface and side surfaces connecting the top surface and the bottom surface. Each of the side surfaces is composed of first side surface extending from the top surface toward the bottom surface, second side surface extending from the first side surface toward the bottom surface, and third side surface extending from the second side surface toward the bottom surface.
    Type: Application
    Filed: March 13, 2003
    Publication date: October 23, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Nitta, Takafumi Nakamura, Kuniaki Konno, Yasuhiko Akaike, Yoshiki Endo, Katsufumi Kondo
  • Patent number: 6548890
    Abstract: A press-contact type semiconductor device comprises: a plurality of semiconductor elements each of which has a first main electrode and a control electrode and a second main electrode; a second common main power source plate having the semiconductor elements positioned on a front surface thereof and electrically connected to the second main electrodes; a first common main power source plate arranged on the front surfaces of the semiconductor elements and electrically connected to the first main electrodes; a common control signal/main current plate arranged between semiconductor elements and including at least control signal wiring layers and main current wiring layers; conductive connectors for electrically connecting at least the main current wiring layers and the first common maim power source plate; and conductive elastic members for electrically connecting the main current wiring layers or the first common main power source plate to the conductive connectors by elasticity.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: April 15, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eitaro Miyake, Yoshiki Endo, Ichiro Omura, Tomokazu Domon
  • Patent number: D508682
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda
  • Patent number: D521952
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Yamada, Kazuhiko Kurahashi, Toshihisa Inoue, Taizo Tomioka, Kazuo Shimokawa, Yoshiki Endo, Masahiro Urase, Osamu Usuda