Abstract: An apparatus control device includes an observed value acquiring unit that acquires, from a sensor that observes an environment in which a control target apparatus is installed, an observed value of the environment, an observation predicted value acquiring unit that gives an observed value acquired to a first learning model and acquires an observation predicted value that is a future observed value from the sensor from the first learning model, and an unobservable value acquiring unit that gives an observed value acquired to a second learning model and acquires an unobservable value that is a value not directly observed by the sensor from the second learning model. In addition, the apparatus control device includes a control value calculating unit that calculates a control value of the control target apparatus using the observed value acquired, the observation predicted value acquired, and the unobservable value acquired.

Abstract: A data analysis apparatus performs to acquire series data having character strings related to an information system to be analyzed as elements and series data having numerical values indicating a state of a device constituting the information system as elements, each of the series data having an index that enables comparison of element order relations within series and between series, classify the elements of each piece of the series data into classification classes, and output series data having classification values indicating classification classes as elements, integrate series data having classification values of the character strings as elements and series data having classification values of the numerical values as elements into one piece of series data, and detect an occurrence of a frequent pattern which is a combination of frequently occurring elements, using the one piece of series data obtained through integration.

Abstract: An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).

Abstract: A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.

Abstract: An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

Abstract: An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).

Abstract: A likelihood generation apparatus for acquiring a likelihood of a 16QAM signal includes a first likelihood generation unit configured to generate a likelihood of each of two bits of a 16QAM signal point of the 16QAM signal from a relationship of each of an I-axis component and a Q-axis component with a likelihood when the 16QAM signal point is mapped on a constellation diagram, and a second likelihood generation unit configured to generate a likelihood of each of remaining two bits other than the two bits of the 16QAM signal point of the 16QAM signal based on a position of the 16QAM signal point in a lookup table, which is configured to input the I-axis component and the Q-axis component of the 16QAM signal point as arguments, and includes regions acquired by dividing the constellation diagram based on a possible value of each of the bits.

Abstract: A likelihood generation apparatus for acquiring a likelihood of a 16QAM signal includes a first likelihood generation unit configured to generate a likelihood of each of two bits of a 16QAM signal point of the 16QAM signal from a relationship of each of an I-axis component and a Q-axis component with a likelihood when the 16QAM signal point is mapped on a constellation diagram, and a second likelihood generation unit configured to generate a likelihood of each of remaining two bits other than the two bits of the 16QAM signal point of the 16QAM signal based on a position of the 16QAM signal point in a lookup table, which is configured to input the I-axis component and the Q-axis component of the 16QAM signal point as arguments, and includes regions acquired by dividing the constellation diagram based on a possible value of each of the bits.

Abstract: A likelihood generation apparatus for acquiring a likelihood of a 16QAM signal includes a first likelihood generation unit configured to generate a likelihood of each of two bits of a 16QAM signal point of the 16QAM signal from a relationship of each of an I-axis component and a Q-axis component with a likelihood when the 16QAM signal point is mapped on a constellation diagram, and a second likelihood generation unit configured to generate a likelihood of each of remaining two bits other than the two bits of the 16QAM signal point of the 16QAM signal based on a position of the 16QAM signal point in a lookup table, which is configured to input the I-axis component and the Q-axis component of the 16QAM signal point as arguments, and includes regions acquired by dividing the constellation diagram based on a possible value of each of the bits.

Abstract: An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

Abstract: A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.

Abstract: A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.

Abstract: Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

Abstract: An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.

Abstract: A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.

Abstract: An error-correction coding method that includes outer coding of performing a coding process for an outer code; and inner coding of performing a coding process for an inner code that has an error correction capability adjusted based on an error correction capability of the outer code.

Abstract: A Sum-product decoder 17 carries out soft-decision iterative decoding on a received signal s?(t) received by a signal receiving unit 12 by using an extended check matrix Hd which is a combination of a matrix D in which differential modulation by a differential modulator 3 is replaced by a check matrix and a check matrix H for error correcting codes to carry out error correction decoding on an information sequence bi.

Abstract: An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.

Abstract: An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.

Abstract: In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.