Abstract: A communication device is provided with a turbo encoder (1) which carries out a turbo encoding process on the lower two bits of transmission data so as to output information bits of two bits and redundant bits of two bits, a conversion (2) which carries out calculations so as to uniform error-correction capabilities on respective information bits by using the output, decoders (11 to 18) which carries out a soft-judgment on the lower two bits of the received signal that are susceptible to degradation in the characteristics so as to estimate the original transmission data, and a second judging device (19) which carries out a hard-judgment on the other bits in the received signal so as to estimate the original transmission data.

Abstract: A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.

Abstract: An RS encoding circuit encodes for error correction bits for information symbols in which information bits are assigned to low-order bits and dummy bits are assigned to high-order bits so as to generate bits for parity symbols such that the number of bits per information symbol is equal to the number of bits per parity symbol. A symbol conversion circuit subjects high-order bits for parity symbols to symbol conversion.

Abstract: A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

Abstract: A demodulation method includes: a coset estimation step for estimating a low-order information bit based on a log-likelihood ratio of the low-order information bit and estimating a parity bit based on a log-likelihood ratio of the parity bit, so as to estimate a coset based on the low-order information bit and the parity bit; and a high-order information bit estimation step for estimating a transmitted signal point based on the coset so as to estimate a high-order information bit based on the transmitted signal point.

Abstract: A communication device is provided with a turbo encoder (1) which carries out a turbo encoding process on the lower two bits of transmission data so as to output two-bit information bits and two-bit redundant bits that are generated so as to uniform the correction capabilities with respect to the respective information bits; a turbo decoder (a first decoder (11), a second decoder (15), etc.) which carries out a soft-judgment on the lower two bits of a received signal that are susceptible to degradation in characteristics, and also carries out an error-correction process using Reed Solomon codes thereon so that the information bits of the lower two bits are estimated, and a third judging device (22) which carries out a hard-judging process on the other bits of the received signal so that the other upper bits are estimated.

Abstract: An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.

Abstract: A communication device is provided with a turbo encoder (1) which carries out a turbo encoding process on the lower two bits of transmission data so as to output two-bit information bits and two-bit redundant bits that are generated so as to uniform the correction capabilities with respect to the respective information bits; a turbo decoder (a first decoder (11), a second decoder (15), etc.) which carries out a soft-judgment on the lower two bits of a received signal that are susceptible to degradation in characteristics, and also carries out an error-correction process using Reed Solomon codes thereon so that the information bits of the lower two bits are estimated, and a third judging device (22) which carries out a hard-judging process on the other bits of the received signal so that the other upper bits are estimated.

Abstract: In the conventional digital radio communications, ½ or more of a channel capacity has been used for error control. Thus, error resistance is high, and a digital compressed moving picture can be transmitted within a short time in the case of high-speed transmission. However, when large-capacity information, such as image data, is transmitted in low bit data transmission, e.g., a digital MCA system, transmission takes a long time even when an error is small on a transmission path. Conversely, a reduction in redundancy shortens transmission time, but reduces error resistance. Consequently, in the case of digital compressed image data, it was impossible to reproduce an image with respect to a 1-bit error. A method is disclosed for protecting data by correcting a plurality of errors.

Abstract: A decoding unit includes a first decoder and a second decoder. The decoding unit further includes an input/output interface for inputting received code sequences, and channel value memories for storing the received codes sequences. Placing prior values at their initial value of zero, the first decoder decodes a first block, and the second decoder decodes a second block of the received code sequences in parallel. Among the decoded results, that is, posterior values and external values, the external values are stored in an external value memory. In the next decoding, the external values are read as prior values. The decoding process is repeated by a predetermined number of times, and posterior values of the final decoded result is output from the input/output interface as the decoded result. The decoding unit can reduce the time required for decoding because of the parallel decoding of the blocks.