Abstract: Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

Abstract: An error correcting device in an optical communication system that transmits a transmission frame formed by adding an overhead and an error correction code to information data uses a concatenated code or an iterated code of at least two error correction codes as an outer code and an error correction code for soft-decision decoding as an inner code.

Abstract: An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.

Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

Abstract: A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

Abstract: An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number<n) and n2 subframes (n2 is a natural number which satisfies n1+n2=n), block-codes the n1 subframes for every m1 subframes (m1 is a factor of n1) so as to generate a first error correction code, and block-codes the n2 subframes for every m2 subframes (m2 is a factor of n2) so as to generate a second error correction code.

Abstract: Provided is an error correction encoding device including: an outer encoding circuit (33) for performing encoding processing for outer code; and an inner encoding circuit (34) for performing encoding processing for inner code, the inner encoding circuit (34) including an inner-encoding input circuit (54) for performing interleaving processing in which a parallel input sequence is divided into given lanes, and a given barrel shift is performed for each inner frame. By carrying out interleaving in which the parallel input sequence is divided into the given lanes, and the given barrel shift is performed for the each inner frame, allocation ratios between an information sequence area and a parity sequence area are made uniform, to thereby improve a processing throughput and enhance an error correction capability.

Abstract: An error correction coding apparatus includes a first coding unit for coding a sequence data to be coded which includes information source data for each frame to generate an error correcting code word sequence including a parity sequences, and a first rearranging unit for rearranging elements of the error correcting code word sequences of a plurality of frames generated by the first coding unit. The first rearranging unit rearranges elements of the parity sequences included in the error correcting code word sequences. The first rearranging unit also rearranges elements of the error correcting code word sequences other than the parity sequences, within the error correcting code word sequences other than the parity sequences.

Abstract: In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.

Abstract: An error-correction coding method that includes outer coding of performing a coding process for an outer code; and inner coding of performing a coding process for an inner code that has an error correction capability adjusted based on an error correction capability of the outer code.

Abstract: An error correcting device in an optical communication system that transmits a transmission frame formed by adding an overhead and an error correction code to information data uses a concatenated code or an iterated code of at least two error correction codes as an outer code and an error correction code for soft-decision decoding as an inner code.

Abstract: A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

Abstract: A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

Abstract: An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number<n) and n2 subframes (n2 is a natural number which satisfies n1+n2=n), block-codes the n1 subframes for every m1 subframes (m1 is a factor of n1) so as to generate a first error correction code, and block-codes the n2 subframes for every m2 subframes (m2 is a factor of n2) so as to generate a second error correction code.

Abstract: An error correction coding apparatus includes a frame generating unit for buffering inputted information sequence data in frame buffers which correspond to units to be coded, respectively, a first interleaving unit for rearranging the information sequence data within two or more of the frame buffers, a first coding unit for coding the information sequence data rearranged by the first interleaving unit for each of the frame buffers, and for buffering an error correcting code generated thereby in the frame buffer, a first deinterleaving unit for rearranging code word sequence data in the frame buffer which is coded by the first coding unit according to a procedure which is reverse to that which the first interleaving unit uses, and a multiplexing unit for outputting, as transmission information, the code word sequence data rearranged by the first deinterleaving unit.

Abstract: A communication device is provided with a turbo encoder (1) which carries out a turbo encoding process on the lower two bits of transmission data so as to output information bits of two bits and redundant bits of two bits, a conversion (2) which carries out calculations so as to uniform error-correction capabilities on respective information bits by using the output, decoders (11 to 18) which carries out a soft-judgment on the lower two bits of the received signal that are susceptible to degradation in the characteristics so as to estimate the original transmission data, and a second judging device (19) which carries out a hard-judgment on the other bits in the received signal so as to estimate the original transmission data.

Abstract: A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

Abstract: An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46?ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.