Patents by Inventor Yoshikuni Tateyama

Yoshikuni Tateyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200118859
    Abstract: A process apparatus includes an electrostatic chuck disposed at a substrate holder. The electrostatic chuck includes a dielectric and an electrode. The electrode is disposed in an interior of the dielectric. The apparatus further includes a circuit electrically connected to the electrode of the electrostatic chuck and a first earth wire electrically connected to the circuit. The first earth wire is shielded by a metal with an electrically insulating cover interposed.
    Type: Application
    Filed: March 12, 2019
    Publication date: April 16, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi SANDA, Kai HU, Hironobu SHIBATA, Koji FUJIBAYASHI, Yoshikuni TATEYAMA, Hideto YABUI
  • Patent number: 8685857
    Abstract: There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 ?m, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 ?m, and a surfactant having a hydrophilic moiety.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano, Atsushi Shigeta
  • Patent number: 8292694
    Abstract: A substrate holding mechanism, a substrate polishing apparatus and a substrate polishing method have functions capable of minimizing an amount of heat generated during polishing of a substrate to be polished and of effectively cooling a substrate holding part of the substrate holding mechanism, and also capable of effectively preventing a polishing solution and polishing dust from adhering to an outer peripheral portion of the substrate holding part and drying thereon. The substrate holding mechanism has a mounting flange, a support member 6 and a retainer ring. A substrate to be polished is held on a lower side of the support member surrounded by the retainer ring, and the substrate is pressed against a polishing surface of a polishing table. The mounting flange is provided with a flow passage contiguous with at least the retainer ring. A temperature-controlled gas is supplied through the flow passage to cool the mounting flange, the support member and the retainer ring.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: October 23, 2012
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Tetsuji Togawa, Toshio Watanabe, Hiroyuki Yano, Gen Toyota, Kenji Iwade, Yoshikuni Tateyama
  • Patent number: 8174125
    Abstract: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for a wire through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire through the second insulating film and extending into the first insulating film spaced from a formed area of the recess for the wire; providing a conductive material inside the recess for the wire and the recess for the dummy wire; and providing a wire inside the recess for the wire and providing a dummy wire inside the recess for the dummy wire by polishing and removing the conductive material.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyuki Kurashima, Gaku Minamihaba, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano
  • Patent number: 8078306
    Abstract: An apparatus polishes an object material such as a film on a substrate. This apparatus includes a polishing table for holding a polishing pad having a polishing surface, a motor configured to drive the polishing table, a holding mechanism configured to hold a substrate having an object material to be polished and to press the substrate against the polishing surface, a dresser configured to dress the polishing surface, and a monitoring unit configured to monitor a removal amount of the object material. The monitoring unit is operable to calculate the removal amount of the object material using a model equation containing a variable representing an integrated value of a torque current of the motor when polishing the object material and a variable representing a cumulative operating time of the dresser.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: December 13, 2011
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Hidetaka Nakao, Eisaku Hayashi, Kunio Oishi, Isao Hayakawa, Yoshiaki Miyake, Yoshikuni Tateyama, Takeshi Ashihara
  • Publication number: 20110250756
    Abstract: A chemical mechanical polishing aqueous dispersion comprises (A) abrasive grains, (B) at least one of quinolinecarboxylic acid and pyridinecarboxylic acid, (C) an organic acid other than quinolinecarboxylic acid and pyridinecarboxylic acid, (D) an oxidizing agent, and (E) a nonionic surfactant having a triple bond, the mass ratio (WB/WC) of the amount (WB) of the component (B) to the amount (WC) of the component (C) being 0.01 or more and less than 2, and the component (E) being shown by the following general formula (1), wherein m and n individually represent integers equal to or larger than one, provided that m+n?50 is satisfied.
    Type: Application
    Filed: June 22, 2011
    Publication date: October 13, 2011
    Applicants: KABUSHIKI KAISHA TOSHIBA, JSR CORPORATION
    Inventors: Kazuhito UCHIKURA, Hirotaka Shida, Yuuichi Hashiguchi, Gaku Minamihaba, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano
  • Publication number: 20110195888
    Abstract: Post-CMP treating liquids are provided, one of which includes water, an amphoteric surfactant, an anionic surfactant, a complexing agent, resin particles having carboxylic group and sulfonyl group on their surfaces, a primary particle diameter thereof ranging from 10 to 60 nm, and tetramethyl ammonium hydroxide. Another includes water, polyphenol, an anionic surfactant, ethylene diamine tetraacetic acid, resin particles having carboxylic group and sulfonyl group on their surfaces, a primary particle diameter thereof ranging from 10 to 60 nm, and tetramethyl ammonium hydroxide. Both of the treating liquids have a pH ranging from 4 to 9, and exhibit a polishing rate both of an insulating film and a conductive film at a rate of 10 nm/min or less.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Inventors: Nobuyuki KURASHIMA, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano
  • Patent number: 7985685
    Abstract: A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kinoshita, Seiro Miyoshi, Yoshikuni Tateyama, Takeshi Nishioka, Hiroyuki Yano
  • Patent number: 7951717
    Abstract: Post-CMP treating liquids are provided, one of which includes water, an amphoteric surfactant, an anionic surfactant, a complexing agent, resin particles having carboxylic group and sulfonyl group on their surfaces, a primary particle diameter thereof ranging from 10 to 60 nm, and tetramethyl ammonium hydroxide. Another includes water, polyphenol, an anionic surfactant, ethylene diamine tetraacetic acid, resin particles having carboxylic group and sulfonyl group on their surfaces, a primary particle diameter thereof ranging from 10 to 60 nm, and tetramethyl ammonium hydroxide. Both of the treating liquids have a pH ranging from 4 to 9, and exhibit a polishing rate both of an insulating film and a conductive film at a rate of 10 nm/min or less.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: May 31, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyuki Kurashima, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano
  • Patent number: 7888139
    Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Takeo Kubota, Yoshikuni Tateyama, Hiroyuki Kanaya, Yoshihiro Minami
  • Patent number: 7883394
    Abstract: A substrate holding mechanism, a substrate polishing apparatus and a substrate polishing method have functions capable of minimizing an amount of heat generated during polishing of a substrate to be polished and of effectively cooling a substrate holding part of the substrate holding mechanism, and also capable of effectively preventing a polishing solution and polishing dust from adhering to an outer peripheral portion of the substrate holding part and drying thereon. The substrate holding mechanism has a mounting flange, a support member 6 and a retainer ring. A substrate to be polished is held on a lower side of the support member surrounded by the retainer ring, and the substrate is pressed against a polishing surface of a polishing table. The mounting flange is provided with a flow passage contiguous with at least the retainer ring. A temperature-controlled gas is supplied through the flow passage to cool the mounting flange, the support member and the retainer ring.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Tetsuji Togawa, Toshio Watanabe, Hiroyuki Yano, Gen Toyota, Kenji Iwade, Yoshikuni Tateyama
  • Publication number: 20100193850
    Abstract: First and second transistors are formed on a substrate. An interlayer insulating film is formed on the first transistor. A first contact is formed in the interlayer film on a source or a drain of the first transistor. A second contact is formed in the interlayer film on the other of the source or the drain. A first interconnect is formed on the first contact. A magnetoresistive element is formed on the second contact. The magnetoresistive element is arranged in a layer having a height equal to that of the first interconnect from a substrate surface. A third contact is formed in the interlayer film on a source or a drain of the second transistor. A second interconnect is formed on the third contact. The second interconnect is arranged in a layer having a height equal to those of the first interconnect and the magnetoresistive element from the substrate surface.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 5, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki ASAO, Takeshi KAJIYAMA, Minoru AMANO, Yoshikuni TATEYAMA, Atsushi SHIGETA
  • Publication number: 20100144062
    Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.
    Type: Application
    Filed: August 27, 2009
    Publication date: June 10, 2010
    Inventors: Yukiteru MATSUI, Takeo Kubota, Yoshikuni Tateyama, Hiroyuki Kanaya, Yoshihiro Minami
  • Publication number: 20100062691
    Abstract: A substrate holding mechanism, a substrate polishing apparatus and a substrate polishing method have functions capable of minimizing an amount of heat generated during polishing of a substrate to be polished and of effectively cooling a substrate holding part of the substrate holding mechanism, and also capable of effectively preventing a polishing solution and polishing dust from adhering to an outer peripheral portion of the substrate holding part and drying thereon. The substrate holding mechanism has a mounting flange, a support member 6 and a retainer ring. A substrate to be polished is held on a lower side of the support member surrounded by the retainer ring, and the substrate is pressed against a polishing surface of a polishing table. The mounting flange is provided with a flow passage contiguous with at least the retainer ring. A temperature-controlled gas is supplied through the flow passage to cool the mounting flange, the support member and the retainer ring.
    Type: Application
    Filed: November 13, 2009
    Publication date: March 11, 2010
    Inventors: Tetsuji TOGAWA, Toshio Watanabe, Hiroyuki Yano, Gen Toyota, Kenji Iwade, Yoshikuni Tateyama
  • Publication number: 20090258493
    Abstract: A substance to be polished made of a silicon oxide film formed on a semiconductor substrate is chemically and mechanically polished and planarized by bringing the substance to be polished into contact with a polishing pad having a modulus of elasticity within a range of 400 to 600 megapascals and by relatively sliding the substance to be polished and the polishing pad, in a condition that a polishing pressure is within a range of 50 to 200 hectopascals and that a rotation number of the polishing pad is within a range of 10 to 80 rpm, and in a state that a polishing slurry containing cerium oxide particles and an anionic surfactant is supplied to the polishing pad.
    Type: Application
    Filed: March 13, 2009
    Publication date: October 15, 2009
    Inventors: Yukiteru MATSUI, Hajime EDA, Takatoshi ONO, Satoko Seta, Yoshikuni TATEYAMA
  • Publication number: 20090184415
    Abstract: A manufacturing method of a semiconductor device comprises: providing a first insulating film whose relative dielectric constant is at most a predetermined value above a substrate; providing a second insulating film whose relative dielectric constant is greater than the predetermined value on a surface of the first insulating film; forming a recess for a wire through the second insulating film and extending into the first insulating film, and also forming a recess for a dummy wire through the second insulating film and extending into the first insulating film spaced from a formed area of the recess for the wire; providing a conductive material inside the recess for the wire and the recess for the dummy wire; and providing a wire inside the recess for the wire and providing a dummy wire inside the recess for the dummy wire by polishing and removing the conductive material.
    Type: Application
    Filed: March 27, 2009
    Publication date: July 23, 2009
    Inventors: Nobuyuki Kurashima, Gaku Minamihaba, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano
  • Publication number: 20090176372
    Abstract: A chemical mechanical polishing slurry includes at least one water-soluble polymer selected from a group consisting of polyacrylic acid, polymethacrylic acid and a salt thereof each having a weight-average molecular weight of 1,000,000 to 10,000,000, ?-cyclodextrin, colloidal silica, and water.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 9, 2009
    Inventors: Gaku MINAMIHABA, Nobuyuki KURASHIMA, Atsushi SHIGETA, Yoshikuni TATEYAMA, Hiroyuki YANO
  • Publication number: 20090156000
    Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a first slurry containing first resin particles and a water-soluble polymer to planarize a surface of the organic film precursor, and polishing the organic film precursor where the surface is planarized using a second slurry containing second resin particles and a water-soluble polymer to leave the organic film precursor in the recess, thereby exposing the insulating film, an average particle diameter of the second resin particles being smaller than that of the first resin particles.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Inventors: Yukiteru MATSUI, Atsushi Shigeta, Yoshikuni Tateyama, Takeshi Nishioka, Hiroyuki Yano
  • Publication number: 20090124076
    Abstract: A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 14, 2009
    Inventors: Yukiteru Matsui, Masako Kinoshita, Seiro Miyoshi, Yoshikuni Tateyama, Takeshi Nishioka, Hiroyuki Yano
  • Publication number: 20090124172
    Abstract: A chemical mechanical polishing aqueous dispersion comprises (A) abrasive grains, (B) at least one of quinolinecarboxylic acid and pyridinecarboxylic acid, (C) an organic acid other than quinolinecarboxylic acid and pyridinecarboxylic acid, (D) an oxidizing agent, and (E) a nonionic surfactant having a triple bond, the mass ratio (WB/WC) of the amount (WB) of the component (B) to the amount (WC) of the component (C) being 0.01 or more and less than 2, and the component (E) being shown by the following general formula (1), wherein m and n individually represent integers equal to or larger than one, provided that m+n?50 is satisfied.
    Type: Application
    Filed: March 27, 2007
    Publication date: May 14, 2009
    Applicants: JSR CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito Uchikura, Hirotaka Shida, Yuuichi Hashiguchi, Gaku Minamihara, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano