Patents by Inventor Yoshinao Miura
Yoshinao Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10410868Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.Type: GrantFiled: January 29, 2018Date of Patent: September 10, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Patent number: 10290583Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.Type: GrantFiled: March 23, 2017Date of Patent: May 14, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshinao Miura
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Patent number: 10229992Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.Type: GrantFiled: February 26, 2018Date of Patent: March 12, 2019Assignee: Renesas Electronics CorporationInventors: Yoshinao Miura, Hironobu Miyamoto
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Patent number: 10135337Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.Type: GrantFiled: April 19, 2017Date of Patent: November 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryohei Nega, Yoshinao Miura
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Patent number: 10134850Abstract: A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.Type: GrantFiled: August 17, 2017Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Yoshinao Miura, Hironobu Miyamoto
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Publication number: 20180308968Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.Type: ApplicationFiled: February 26, 2018Publication date: October 25, 2018Applicant: Renesas Electronics CorporationInventors: Yoshinao MIURA, Hironobu MIYAMOTO
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Patent number: 10032736Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.Type: GrantFiled: September 23, 2014Date of Patent: July 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinao Miura, Takashi Nakamura, Tadatoshi Danno
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Patent number: 10014403Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.Type: GrantFiled: February 21, 2017Date of Patent: July 3, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
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Publication number: 20180151377Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.Type: ApplicationFiled: January 29, 2018Publication date: May 31, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Patent number: 9984884Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.Type: GrantFiled: December 20, 2016Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
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Publication number: 20180097070Abstract: A semiconductor device includes a channel layer formed over a substrate, a barrier layer formed on the channel layer and a gate electrode. A second gate electrode section is formed on the gate electrode via a gate insulating film. It becomes possible to make an apparent threshold voltage applied to the second gate electrode of a MISFET higher than an original threshold voltage applied to the gate electrode for forming a channel under the gate electrode by providing an MIM section configured by the gate electrode, the gate insulating film and the second gate electrode in this way.Type: ApplicationFiled: August 17, 2017Publication date: April 5, 2018Applicant: Renesas Electronics CorporationInventors: Yoshinao MIURA, Hironobu MIYAMOTO
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Patent number: 9837519Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.Type: GrantFiled: November 8, 2016Date of Patent: December 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
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Patent number: 9793196Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.Type: GrantFiled: November 2, 2016Date of Patent: October 17, 2017Assignee: Renesas Electronics CorporationInventors: Akira Matsumoto, Yoshinao Miura, Yasutaka Nakashiba
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Publication number: 20170278798Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.Type: ApplicationFiled: March 23, 2017Publication date: September 28, 2017Inventor: Yoshinao MIURA
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Publication number: 20170271326Abstract: A semiconductor device includes a substrate, a plurality of transistors formed on a transistor region of the substrate, a plurality of diodes formed on a diode region of the substrate, the transistors and the diodes being arranged in a first direction, a first line formed over the substrate and extending between the transistors and the diodes, a plurality of first branch lines extending from the first line in the first direction to form a drain electrode of the transistors, and a plurality of second branch lines extending from the first line in the first direction to form an anode electrode of the diodes.Type: ApplicationFiled: May 31, 2017Publication date: September 21, 2017Inventor: Yoshinao MIURA
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Patent number: 9748225Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.Type: GrantFiled: December 16, 2015Date of Patent: August 29, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinao Miura, Hironobu Miyamoto, Yasuhiro Okamoto
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Publication number: 20170222559Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Ryohei Nega, Yoshinao Miura
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Patent number: 9691757Abstract: Reduction of the speed of switching between the drain electrodes of transistors and the cathode electrodes of diodes due to the inductances of lines coupling them is inhibited. Transistors and diodes are formed over a substrate. The transistors and the diodes are arranged in a first direction. The substrate also includes a first line, first branch lines, and second branch lines formed thereover. The first line extends between the transistors and the diodes. The first branch lines are formed to branch from the first line in a direction to overlap the transistors and are coupled to the transistors. The second branch lines are formed to branch from the first line in a direction to overlap the diodes and are coupled to the diodes.Type: GrantFiled: June 27, 2015Date of Patent: June 27, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshinao Miura
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Publication number: 20170162683Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Yoshinao MIURA, Takashi INOUE
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Patent number: 9667147Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.Type: GrantFiled: March 9, 2016Date of Patent: May 30, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryohei Nega, Yoshinao Miura