Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Abstract: A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF.

Abstract: Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.

Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.

Abstract: The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate.

Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

Abstract: A semiconductor device has a semiconductor substrate, and a parallel p-n layer provided between the main surface and the back surface of the semiconductor substrate, and first-conductivity-type drift region and second-conductivity-type partition regions alternately arranged therein, wherein in the parallel p-n layer, the second-conductivity-type partition regions are periodically formed conforming to a basic periodicity specified by a predetermined distance, and SA/S (where, SA is a sectional area per a single second-conductivity-type partition region as viewed in a plane parallel with the main surface, and S is a sectional area of a unit structural region, periodically formed as containing one of the second-conductivity-type partition regions, as viewed in a plane parallel with the main surface) in an element-forming region allowing current to flow therethrough is smaller than SA/S in at least a portion of a periphery region surrounding the element-forming region.

Abstract: Aiming at realizing high breakdown voltage and low ON resistance of a semiconductor device having the super-junction structure, the semiconductor device of the present invention has a semiconductor substrate having an element forming region having a gate electrode formed therein, and a periphery region formed around the element forming region, and having an field oxide film formed therein; and a parallel p-n layer having n-type drift regions and p-type column regions alternately arranged therein, formed along the main surface of the semiconductor substrate, as being distributed over the element forming region and a part of the periphery region, wherein the periphery region has no column region formed beneath the end portion on the element forming region side of the field oxide film and has p-type column regions as at least one column region formed under the field oxide film.

Abstract: A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel.

Abstract: A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the semiconductor substrate 101, there is formed a parallel pn layer having an N-type drift region 104 and P-type column regions 106 alternately arranged therein. In the circumferential region, there is formed a field electrode 120, but the field electrode 120 is not formed on the P-type column regions 106. The P-type column regions 106 in the circumferential region are formed with a depth larger than or equal to that of the P-type column regions 106 in the element-forming region.

Abstract: A semiconductor device is provided with a vertical MOSFET including an N-type drift region that has a {110} crystal plane serving as the main surface thereof, a trench gate structure formed in a trench that has a {100} crystal plane serving as a sidewall surface thereof, and plural P-type column region structures provided in the N-type drift region 3, making up the super-junction structure. The P-type column region structures are disposed so as to be separated from each other in a plan view, and each of the plurality of column structures includes a plurality of column regions of the second conductivity type separated from each other in a cross-sectional view. By applying ion implantation of a P-type dopant to the main surface from a direction vertical to the main surface, the P-type column regions are formed down to sufficiently deeper positions in the drift region due to channeling. By so doing, it is possible to obtain a semiconductor device with an enhanced breakdown voltage.

Abstract: A semiconductor apparatus includes a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed on a principal surface of the semiconductor substrate, a trench formed in a periphery of the base region, and an endless source region of the first conductivity type formed on a surface of the base region along the trench. In this semiconductor apparatus, the principal planes on side surfaces of the trench are composed of planes [100] and [110]. The interior angle of intersection of adjacent side surfaces of the trench is 135°. A minimum distance between the base region and the plane [110] facing each other through the source region is shorter than a minimum distance between the base region and the plane [100] facing each other through the source region.

Abstract: A semiconductor apparatus comprises a gate electrode, a gate insulating layer, a drift region of a first conductivity type formed over a semiconductor substrate of the first conductivity type, a base region of a second conductivity type formed over the drift region, a source region of the first conductivity type formed on the base region and a column region formed in the drift region under the base region, the column region being divided into a plurality of divided portions in depth direction.