Patents by Inventor Yoshinobu Asami

Yoshinobu Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170213598
    Abstract: Provided is a highly integrated semiconductor device which can hold data and includes a NAND cell array. Each of the plurality of memory cells of the NAND cell array includes a first transistor, a second transistor, a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal is electrically connected to one electrode connected to a channel region of the first transistor. The second terminal is electrically connected to the other electrode connected to the channel region of the first transistor. The third terminal is electrically connected to a gate electrode of the second transistor. The fourth terminal is electrically connected to one electrode connected to a channel region of the second transistor. A gate electrode of the first transistor is in contact with the other electrode connected to the channel region of the second transistor. A string of the plurality of memory cells is formed by connecting the first terminals and the second terminals.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 27, 2017
    Inventor: Yoshinobu ASAMI
  • Publication number: 20160284859
    Abstract: A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Inventor: Yoshinobu ASAMI
  • Publication number: 20160268436
    Abstract: A highly integrated semiconductor device that holds data and includes a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the second semiconductor layer is substantially aligned with an end portion of the conductive layer.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 15, 2016
    Inventor: Yoshinobu ASAMI
  • Publication number: 20160240684
    Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 18, 2016
    Inventors: Shunpei YAMAZAKI, Yoshinobu ASAMI, Yutaka OKAZAKI, Motomu KURATA, Katsuaki TOCHIBAYASHI, Shinya SASAGAWA, Kensuke YOSHIZUMI, Hideomi SUZAWA
  • Publication number: 20160233340
    Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 11, 2016
    Inventors: Akihisa SHIMOMURA, Satoru OKAMOTO, Yutaka OKAZAKI, Yoshinobu ASAMI, Hiroaki HONDA, Takuya TSURUME
  • Publication number: 20160218219
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 28, 2016
    Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
  • Patent number: 9263404
    Abstract: A lot of buildings have been built while it is concerned that a building material is used fraudulently. Therefore, the present invention provides a managing method of the material and a system thereof. The present invention provides a managing method including a step of attaching a sheet including a plurality of memories to each surface of a plurality of materials, a step of dividing the plurality of materials with the sheet in accordance with data in the memory, a step of constructing a building by using the divided material in accordance with the data in the memory, and a step of checking the data on the constructed building, which is stored in the plurality of memories.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: February 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Publication number: 20160005740
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Application
    Filed: September 3, 2015
    Publication date: January 7, 2016
    Inventors: Yoshinobu ASAMI, Tamae TAKANO, Masayuki SAKAKURA, Ryoji NOMURA, Shunpei YAMAZAKI
  • Patent number: 9231070
    Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Tetsuhiro Tanaka, Yoshinobu Asami
  • Patent number: 9159793
    Abstract: An oxide semiconductor material having p-type conductivity and a semiconductor device using the oxide semiconductor material are provided. The oxide semiconductor material having p-type conductivity can be provided using a molybdenum oxide material containing molybdenum oxide (MoOy (2<y<3)) having an intermediate composition between molybdenum dioxide and molybdenum trioxide. For example, a semiconductor device is formed using a molybdenum oxide material containing molybdenum trioxide (MoO3) as its main component and MoOy (2<y<3) at 4% or more.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: October 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Riho Kataishi, Erumu Kikuchi
  • Patent number: 9129866
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Tamae Takano, Masayuki Sakakura, Ryoji Nomura, Shunpei Yamazaki
  • Patent number: 9112086
    Abstract: To provide a photoelectric conversion device which has little light loss caused by light absorption in a window layer and has favorable electric characteristics. The photoelectric conversion device includes, between a pair of electrodes, a light-transmitting semiconductor layer which has one conductivity type and serves as a window layer, and a silicon semiconductor substrate having a conductivity type for forming a p-n junction or a silicon semiconductor layer having a conductivity type for forming a p-i-n junction. The light-transmitting semiconductor layer can be formed using an inorganic compound containing, as its main component, an oxide of a metal belonging to any of Groups 4 to 8 of the periodic table. The band gap of the metal oxide is greater than or equal to 2 eV.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Riho Kataishi, Yoshinobu Asami
  • Patent number: 9048356
    Abstract: A photoelectric conversion device includes a first cell including a photoelectric conversion layer, a second cell over the first cell including a photoelectric conversion layer formed of a material having a wider band gap than that of the first cell, first and second electrodes under a surface of the first cell which is opposite to the second cell, and a third electrode over a surface of the second cell which is opposite to the first cell. The first and second cells each include a p-n or p-i-n junction, the first and second cells are in contact with each other and a p-n junction is formed in a contact portion therebetween, the first cell is electrically connected to the first and second electrodes to form a back contact structure, and the second cell is electrically connected to the third electrode.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8994009
    Abstract: To provide a photoelectric conversion device which has little light loss caused by light absorption in a window layer, the photoelectric conversion device includes a first electrode, a first semiconductor layer formed over the first electrode, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, and a second electrode formed over the third semiconductor layer; and the first semiconductor layer is a light-transmitting semiconductor layer containing an organic compound and an inorganic compound, and the second semiconductor layer and the third semiconductor layer are each a semiconductor layer containing an organic compound.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Riho Kataishi
  • Publication number: 20150001535
    Abstract: An oxide semiconductor material having p-type conductivity and a semiconductor device using the oxide semiconductor material are provided. The oxide semiconductor material having p-type conductivity can be provided using a molybdenum oxide material containing molybdenum oxide (MoOy (2<y<3)) having an intermediate composition between molybdenum dioxide and molybdenum trioxide. For example, a semiconductor device is formed using a molybdenum oxide material containing molybdenum trioxide (MoO3) as its main component and MoOy (2<y<3) at 4% or more.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 1, 2015
    Inventors: Yoshinobu Asami, Riho KATAISHI, Erumu KIKUCHI
  • Publication number: 20140346505
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Yoshinobu ASAMI, Tamae TAKANO, Masayuki SAKAKURA, Ryoji NOMURA, Shunpei YAMAZAKI
  • Patent number: 8889490
    Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8872251
    Abstract: An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8865511
    Abstract: It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semiconductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over a first conductive layer and a second conductive layer over the organic compound layer including an insulator. Further, the semiconductor device is manufactured by forming a first conductive layer, discharging a composition of an insulator and an organic compound over the first conductive layer to form an organic compound layer including an insulator, and forming a second conductive layer over the organic compound layer including an insulator.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Nobuharu Ohsawa, Ryoji Nomura, Yoshinobu Asami
  • Patent number: 8804404
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Tamae Takano, Masayuki Sakakura, Ryoji Nomura, Shunpei Yamazaki