Patents by Inventor Yoshinobu Asami

Yoshinobu Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8212302
    Abstract: A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: July 3, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Patent number: 8198666
    Abstract: A nonvolatile memory element which is provided with a floating gate electrode and a high withstand voltage transistor which is provided with a thick gate insulating film are formed over one substrate without increase in a driving voltage of the nonvolatile memory element. A stacked film of a first insulating film and a second insulating film is formed between an island-like semiconductor region and a floating gate electrode of the nonvolatile memory element and between an island-like semiconductor region and a gate electrode of the transistor. The first insulating film overlapping with the floating gate electrode is removed, and the insulating film between the island-like semiconductor region and the floating gate electrode is formed thinner than the gate insulating film of the transistor.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Manabu Sato
  • Patent number: 8193574
    Abstract: To reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating gate and a control gate. In addition, a second island-shaped semiconductor region is formed under the floating gate with an insulating film interposed therebetween. Since the second island-shaped semiconductor region is electrically connected to the control gate, a capacitance is formed between the second island-shaped semiconductor region and the floating gate. This capacitance contributes to an increase in the coupling ratio of the memory transistor, which makes it possible to increase the coupling ratio without increasing the area of the memory cell. Furthermore, the area of the memory cell can be reduced without reducing the coupling ratio.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8188535
    Abstract: An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Publication number: 20120118352
    Abstract: A reflection member is provided for a space between photoelectric conversion cells or a periphery of the photoelectric conversion cells, which is the place not provided with the photoelectric conversion cell, so that a peak portion of the reflection member is higher than a surface of the photoelectric conversion cells. Accordingly; light having entered the space between the photoelectric conversion cells or the periphery of the photoelectric conversion cells, which does not contribute to power generation under normal circumstances, can be guided to the photoelectric conversion cell through reflection by the reflection member. Note that since the peak portion of the reflection member is higher than the surface of the photoelectric conversion cells, sunlight can be guided to the photoelectric conversion cell through one-time reflection, whereby the object can be achieved.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 17, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshinobu Asami
  • Publication number: 20120108029
    Abstract: It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semiconductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over a first conductive layer and a second conductive layer over the organic compound layer including an insulator. Further, the semiconductor device is manufactured by forming a first conductive layer, discharging a composition of an insulator and an organic compound over the first conductive layer to form an organic compound layer including an insulator, and forming a second conductive layer over the organic compound layer including an insulator.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mikio YUKAWA, Nobuharu OHSAWA, Ryoji NOMURA, Yoshinobu ASAMI
  • Patent number: 8101943
    Abstract: It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semi-conductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over a first conductive layer and a second conductive layer over the organic compound layer including an insulator. Further, the semiconductor device is manufactured by forming a first conductive layer, discharging a composition of an insulator and an organic compound over the first conductive layer to form an organic compound layer including an insulator, and forming a second conductive layer over the organic compound layer including an insulator.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: January 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Nobuharu Ohsawa, Ryoji Nomura, Yoshinobu Asami
  • Publication number: 20110308590
    Abstract: A novel photoelectric conversion device in which energy of light can be effectively utilized and performance can be improved is provided. A photoelectric conversion device includes a photoelectric conversion element and an energy conversion layer provided on a light-receiving side of a photoelectric conversion layer included in the photoelectric conversion element. The energy conversion layer includes a plurality of first layers and a plurality of second layers. The first layer and the second layer are alternately stacked. The thickness of the first layer is greater than or equal to 0.5 nm and less than or equal to 10 nm, and the thickness of the second layer is greater than or equal to 0.5 nm and less than or equal to 10 nm. The second layer can be formed using a material having a larger energy band gap than that of a material used for the first layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Inventors: Yoshinobu Asami, Tomokazu Yokoi
  • Publication number: 20110308568
    Abstract: A photoelectric conversion device includes a first cell including a photoelectric conversion layer, a second cell over the first cell including a photoelectric conversion layer formed of a material having a wider band gap than that of the first cell, first and second electrodes under a surface of the first cell which is opposite to the second cell, and a third electrode over a surface of the second cell which is opposite to the first cell. The first and second cells each include a p-n or p-i-n junction, the first and second cells are in contact with each other and a p-n junction is formed in a contact portion therebetween, the first cell is electrically connected to the first and second electrodes to form a back contact structure, and the second cell is electrically connected to the third electrode.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Inventor: Yoshinobu Asami
  • Publication number: 20110272752
    Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshinobu ASAMI
  • Publication number: 20110263087
    Abstract: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate electrode, generated due to the floating gate electrode.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 27, 2011
    Inventor: Yoshinobu Asami
  • Patent number: 8030643
    Abstract: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Tamae Takano, Masayuki Sakakura, Ryoji Nomura, Shunpei Yamazaki
  • Publication number: 20110227139
    Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 22, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuya KAKEHATA, Tetsuhiro TANAKA, Yoshinobu ASAMI
  • Patent number: 8022460
    Abstract: An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20110210412
    Abstract: On object of the invention is to provide a nonvolatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is to provide a highly-reliable, inexpensive, and nonvolatile memory device and a semiconductor device including the memory device. A memory element includes a first conductive layer, a second conductive layer, a first insulating layer with a thickness of 0.1 nm or more and 4 nm or less being in contact with the first conductive layer, and an organic compound layer interposed between the first conductive layer, the first insulating layer, and the second conductive layer.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mikio YUKAWA, Nobuharu OHSAWA, Yoshinobu ASAMI
  • Patent number: 7994000
    Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 7968932
    Abstract: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating-film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate-electrode, generated due to the floating gate electrode.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 7956352
    Abstract: On object of the invention is to provide a non-volatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is to provide a highly-reliable, inexpensive, and nonvolatile memory device and a semiconductor device including the memory device. A memory element includes a first conductive layer, a second conductive layer, a first insulating layer with a thickness of 0.1 nm or more and 4 nm or less being in contact with the first conductive layer, and an organic compound layer interposed between the first conductive layer, the first insulating layer, and the second conductive layer.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Nobuharu Ohsawa, Yoshinobu Asami
  • Patent number: 7955995
    Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Tetsuhiro Tanaka, Yoshinobu Asami
  • Patent number: 7842992
    Abstract: It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 30, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno