Patents by Inventor Yoshinobu Nakada

Yoshinobu Nakada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7521381
    Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: April 21, 2009
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki
  • Patent number: 7481888
    Abstract: In this heat treatment jig and method for silicon wafers, a silicon wafer is heat-treated while being mounted on support projections provided on three support arms, having an intervening spacing, protruding from a support frame towards the center. At that time, all the support projections under the silicon wafer are positioned on a same circle within a region where a radial distance from the center is defined by 85 to 99.5% of the wafer radius, and the support arms form an angle of 120° with each other about the center. With this jig and method, free depth of a dislocation generated from a pin position can be controlled deeper than a device formation region, and a widest slip-free region where the surface is free from slip dislocation is obtained.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: January 27, 2009
    Assignee: Sumco Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki, Takeshi Hasegawa
  • Publication number: 20070075403
    Abstract: The functional structural element includes: a substrate member which has a surface made of directionally solidified silicon; and a functional structural body which is made of a functional material and is formed on the surface of the substrate member.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 5, 2007
    Inventors: Yukio Sakashita, Takamichi Fujii, Yoshinobu Nakada, Yoshikazu Hishinuma
  • Publication number: 20070076051
    Abstract: The liquid ejection head has a liquid ejection device which ejects liquid and is partially formed of a directionally solidified silicon substrate.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 5, 2007
    Inventors: Takamichi Fujii, Yoshinobu Nakada, Yukio Sakashita, Yoshikazu Hishinuma
  • Patent number: 7199057
    Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: April 3, 2007
    Assignee: Sumco Corporation
    Inventors: So Ik Bae, Yoshinobu Nakada, Kenichi Kaneko
  • Patent number: 7122082
    Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm?3 and 1×1011 cm?3.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: October 17, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Takaaki Shiota, Yoshinobu Nakada
  • Publication number: 20060208434
    Abstract: In this heat treatment jig and method for silicon wafers, a silicon wafer is heat-treated while being mounted on support projections provided on three support arms, having an intervening spacing, protruding from a support frame towards the center. At that time, all the support projections under the silicon wafer are positioned on a same circle within a region where a radial distance from the center is defined by 85 to 99.5% of the wafer radius, and the support arms form an angle of 120° with each other about the center. With this jig and method, free depth of a dislocation generated from a pin position can be controlled deeper than a device formation region, and a widest slip-free region where the surface is free from slip dislocation is obtained.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 21, 2006
    Applicant: Sumco Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki, Takeshi Hasegawa
  • Publication number: 20060148249
    Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.
    Type: Application
    Filed: August 28, 2003
    Publication date: July 6, 2006
    Applicant: Sumco Corporation
    Inventors: So Bae, Yoshinobu Nakada, Kenichi Kaneko
  • Publication number: 20050130452
    Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Application
    Filed: February 9, 2005
    Publication date: June 16, 2005
    Applicant: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki
  • Publication number: 20040207048
    Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm−3 and 1×1011 cm−3.
    Type: Application
    Filed: November 13, 2003
    Publication date: October 21, 2004
    Applicant: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Takaaki Shiota, Yoshinobu Nakada
  • Publication number: 20040053516
    Abstract: Silicon wafer W is thermal-annealed in atmosphere G to form new vacancies therein in a thermal annealing step and atmosphere G in the thermal annealing step contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Application
    Filed: May 28, 2003
    Publication date: March 18, 2004
    Inventors: Yoshinobu Nakada, Hiroyuka Shiraki
  • Publication number: 20040025983
    Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute. ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is an axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting point of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperatures in a range of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, tree of COP's, and substantially free of contamination such as Fe and of occurrence of slip, is obtained.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 12, 2004
    Inventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata
  • Patent number: 6663708
    Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is and axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: December 16, 2003
    Assignee: Mitsubishi Materials Silicon Corporation
    Inventors: Etsuro Morita, Takaaki Shiota, Yoshihisa Nonogaki, Yoshinobu Nakada, Hisashi Furuya, Hiroshi Koya, Jun Furukawa, Hideo Tanaka, Yuji Nakata
  • Patent number: 6540828
    Abstract: A simple and inexpensive method and apparatus for producing crystalline silicon comprising the steps of melting silicon in a mold, then cooling the bottom of the mold is cooled to create a positive temperature gradient from the bottom of the mold upward, thereby causing the molten silicon to crystallize from the inner bottom of the mold upward so that the solid-liquid phase boundary, separating the crystallized silicon from the molten silicon, moves upward as the molten silicon crystallizes. As the silicon crystallizes, an inert gas is blown onto the surface of the molten silicon from a position above the surface of the molten silicon, thereby vibrating the surface of the molten silicon in such a manner that cavities are formed in the surface of the molten silicon.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: April 1, 2003
    Assignee: Mitsubishi Materials Corporation
    Inventors: Saburo Wakita, Yoshinobu Nakada, Junichi Sasaki, Yuji Ishiwari
  • Publication number: 20020139297
    Abstract: A simple and inexpensive method and apparatus for producing crystalline silicon comprising the steps of melting silicon in a mold, then cooling the bottom of the mold is cooled to create a positive temperature gradient from the bottom of the mold upward, thereby causing the molten silicon to crystallize from the inner bottom of the mold upward so that the solid-liquid phase boundary, separating the crystallized silicon from the molten silicon, moves upward as the molten silicon crystallizes. As the silicon crystallizes, an inert gas is blown onto the surface of the molten silicon from a position above the surface of the molten silicon, thereby vibrating the surface of the molten silicon in such a manner that cavities are formed in the surface of the molten silicon.
    Type: Application
    Filed: March 25, 2002
    Publication date: October 3, 2002
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Saburo Wakita, Yoshinobu Nakada, Junichi Sasaki, Yuji Ishiwari
  • Patent number: 6383285
    Abstract: A simple and inexpensive method and apparatus for producing crystalline silicon comprising the steps of melting silicon in a mold, then cooling the bottom of the mold is cooled to create a positive temperature gradient from the bottom of the mold upward, thereby causing the molten silicon to crystallize from the inner bottom of the mold upward so that the solid-liquid phase boundary, separating the crystallized silicon from the molten silicon, moves upward as the molten silicon crystallizes. As the silicon crystallizes, an inert gas is blown onto the surface of the molten silicon from a position above the surface of the molten silicon, thereby vibrating the surface of the molten silicon in such a manner that cavities are formed in the surface of the molten silicon.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: May 7, 2002
    Assignee: Mitsubishi Materials Corporation
    Inventors: Saburo Wakita, Yoshinobu Nakada, Junichi Sasaki, Yuji Ishiwari
  • Patent number: 6378835
    Abstract: A method for producing a silicon ingot having a directional solidification structure comprising the steps of: placing a silicon raw material into a crucible of a melting device constructed by mounting a chill plate on an underfloor heater, mounting a crucible with a large cross-sectional area on the chill plate, providing an overhead heater over the crucible, and surrounding the circumference of the crucible with a heat insulator; heat-melting the silicon raw material by flowing an electric current through the underfloor heater and overhead heater; chilling the bottom of the crucible by halting the electric current through the underfloor heater after the silicon raw material has been completely melted to form a molten silicon; chilling the bottom of the crucible by flowing an inert gas through the chill plate; and intermittently or continuously lowering the temperature of the overhead heater by intermittently or continuously decreasing the electric current through the overhead heater, and an apparatus for pro
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: April 30, 2002
    Assignee: Mitsubishi Materials Corporation
    Inventors: Saburo Wakita, Akira Mitsuhashi, Yoshinobu Nakada, Jun-ichi Sasaki, Yuhji Ishiwari
  • Publication number: 20010032708
    Abstract: An electrode plate which can provide a uniformly-etched surface to an etching surface of a plate to be etched is disclosed, which is used for a plasma etching equipment having such a structure that an electrode plate having a plurality of small vertical through holes is arranged opposite to an etching surface at a prescribed distance from the etching surface, and an etching gas which is introduced into the plasma etching equipment is jetted from the small vertical through holes of the electrode plate and plasma is generated between the etching surface and the surface of the electrode plate to carry out etching, and is characterized in that the electrode plate is composed of high-pure silicon having a cast structure which is formed by a unidirectional solidification perpendicular to the etching surface, thereby to make it possible to form a uniformly-etched surface.
    Type: Application
    Filed: May 30, 2001
    Publication date: October 25, 2001
    Applicant: Mitsubishi Materials Corporation
    Inventors: Akifumi Mishima, Toshiharu Hiji, Yoshinobu Nakada, Tamotsu Mori
  • Patent number: 6299682
    Abstract: A method for producing a silicon ingot having a directional solidification structure comprising the steps of: placing a silicon raw material into a crucible of a melting device constructed by mounting a chill plate on an underfloor heater, mounting a crucible with a large cross-sectional area on the chill plate, providing an overhead heater over the crucible, and surrounding the circumference of the crucible with a heat insulator; heat-melting the silicon raw material by flowing an electric current through the underfloor heater and overhead heater; chilling the bottom of the crucible by halting the electric current through the underfloor heater after the silicon raw material has been completely melted to form a molten silicon; chilling the bottom of the crucible by flowing an inert gas through the chill plate; and intermittently or continuously lowering the temperature of the overhead heater by intermittently or continuously decreasing the electric current through the overhead heater, and an apparatus for pro
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: October 9, 2001
    Assignee: Mitsubishi Materials Corporation
    Inventors: Saburo Wakita, Akira Mitsuhashi, Yoshinobu Nakada, Jun-ichi Sasaki, Yuhji Ishiwari
  • Patent number: 5130260
    Abstract: A method of gettering unintentional mobile impurities starts with production of an damaged portion on the reverse side of a silicon wafer, and the silicon wafer is placed in a high temperature vacuum ambience so that the unintentional mobile impurities are firstly trapped by the damaged portion and, then, evacuated to the high temperature vacuum ambience.
    Type: Grant
    Filed: July 12, 1991
    Date of Patent: July 14, 1992
    Assignees: Mitsubishi Materials Corporation, Nippon Silicon Kabushiki Kaisha
    Inventors: Hisaaki Suga, Yoshinobu Nakada, Kazuhiro Akiyama, Shunji Ishibashi