Abstract: A semiconductor memory device, including a memory cell including a flip-flop, and a memory cell power supply circuit for supplying a cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period.

Abstract: A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state. The word line drivers each have a transistor for causing the corresponding word line to go into the active state. The pull-down circuits each have a pull-down transistor for pulling down the corresponding word line, the pull-down transistor being a transistor having the same conductivity type as that of the transistor included the word line driver for driving the corresponding word line.

Abstract: A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in case where the cell power supply voltage in supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Abstract: A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Abstract: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

Abstract: A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential (e.g., 0 V), a capacitance element for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential (e.g., a negative potential) that is lower than the first potential, and a clamp circuit for clamping the second potential when a power supply voltage becomes high.

Abstract: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

Abstract: A semiconductor integrated circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines corresponding to respective rows of the plurality of memory cells, a plurality of word line drivers for driving the plurality of word lines, respectively, and a plurality of pull-down circuits connected to the plurality of word lines, respectively, for causing voltages of the respective connected word lines to be lower than or equal to a power supply voltage when the respective word lines are in an active state. The word line drivers each have a transistor for causing the corresponding word line to go into the active state. The pull-down circuits each have a pull-down transistor for pulling down the corresponding word line, the pull-down transistor being a transistor having the same conductivity type as that of the transistor included the word line driver for driving the corresponding word line.

Abstract: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.

Abstract: When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the leak current, it is possible to reduce the power consumption of a semiconductor memory device and to increase the operating speed thereof. Moreover, the threshold voltage of transistors in the memory cell is kept low, thereby improving the operating characteristics of the semiconductor memory device at low power supply voltages.

Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Abstract: There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.

Abstract: In a semiconductor memory device, comprising: a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell, the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Abstract: In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

Abstract: A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.

Abstract: A semiconductor memory device, including a memory cell including a flip-flop, and a memory cell power supply circuit for supplying a cell power supply voltage to the memory cell, wherein the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period.

Abstract: There provided a semiconductor memory device which ensures writing to all memory cells regardless of fluctuations in properties of the memory cells caused by manufacturing error or the like and can reduce write operation time and power consumption. Write operations for a memory cell 1 and a dummy memory cell 1a are controlled based on a write amplifier control signal WAE. Write operation end timing is determined based on a write completion signal WRST which indicates a storage state of the dummy memory cell 1a. The dummy memory cell 1a and peripheral circuitry are designed so that write time required for the dummy memory cell 1a is more than or equal to a maximum of write time required for the memory cells 1.

Abstract: A semiconductor integrated circuit has a word line, a pair of bit lines, a memory cell disposed on an intersection of the word line and the pair of bit lines, a precharge circuit for precharging the pair of bit lines at a first voltage, and a sense amplifier circuit for amplifying a potential difference of the pair of bit lines at a second voltage. The first voltage is substantially equal to an on voltage of the sense amplifier circuit, the on voltage being obtained by adding an offset voltage of the sense amplifier circuit to an on voltage of a transistor constituting the sense amplifier circuit, or the first voltage is a voltage between the on voltage of the sense amplifier circuit and the second voltage.