Abstract: A semiconductor memory device includes word lines, bit line pairs, memory cells 1, bit line precharge circuits 2, and write amplifiers 3, as well as a dummy word line, a dummy bit line pair, dummy memory cells 1a, 1b, and 1c, and a memory cell storing node detection circuit 6. Through the action of the dummy memory cells 1b and 1c, it is ensured that the write timing for the dummy memory cell 1a is substantially identical to the write timing for the memory cells 1. Based on changes in the states of storing nodes S1 and S2 included in the dummy memory cell 1a, the memory cell storing node detection circuit 6 generates a write completion signal WRST. As a result, a semiconductor memory device having an optimized write timing and low power consumption is provided.

Abstract: When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the leak current, it is possible to reduce the power consumption of a semiconductor memory device and to increase the operating speed thereof. Moreover, the threshold voltage of transistors in the memory cell is kept low, thereby improving the operating characteristics of the semiconductor memory device at low power supply voltages.

Abstract: The semiconductor memory device comprises a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to the above-mentioned plurality of word lines and the above-mentioned plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to respective one ends of the above-mentioned plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of the above-mentioned plurality of word lines, each of the above-mentioned plurality of first word-line control circuits receiving a signal level of a corresponding one of the above-mentioned plurality of word lines.

Abstract: A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

Abstract: A semiconductor integrated circuit has a word line, a pair of bit lines, a memory cell disposed on an intersection of the word line and the pair of bit lines, a precharge circuit for precharging the pair of bit lines at a first voltage, and a sense amplifier circuit for amplifying a potential difference of the pair of bit lines at a second voltage. The first voltage is substantially equal to an on voltage of the sense amplifier circuit, the on voltage being obtained by adding an offset voltage of the sense amplifier circuit to an on voltage of a transistor constituting the sense amplifier circuit, or the first voltage is a voltage between the on voltage of the sense amplifier circuit and the second voltage.

Abstract: A semiconductor memory device includes word lines, bit line pairs, memory cells 1, bit line precharge circuits 2, and write amplifiers 3, as well as a dummy word line, a dummy bit line pair, dummy memory cells 1a, 1b, and 1c, and a memory cell storing node detection circuit 6. Through the action of the dummy memory cells 1b and 1c, it is ensured that the write timing for the dummy memory cell 1a is substantially identical to the write timing for the memory cells 1. Based on changes in the states of storing nodes S1 and S2 included in the dummy memory cell 1a, the memory cell storing node detection circuit 6 generates a write completion signal WRST. As a result, a semiconductor memory device having an optimized write timing and low power consumption is provided.

Abstract: The semiconductor memory device comprises a plurality of word lines including one or more redundant word lines; a plurality of pairs of bit lines; a plurality of memory cells connected to the above-mentioned plurality of word lines and the above-mentioned plurality of pairs of bit lines; a plurality of word-line drivers, each of which is connected to respective one ends of the above-mentioned plurality of word lines and controlled by a plurality of word-line control signals; and a plurality of first word-line control circuits respectively located at the other ends of the above-mentioned plurality of word lines, each of the above-mentioned plurality of first word-line control circuits receiving a signal level of a corresponding one of the above-mentioned plurality of word lines, wherein, in the case where the signal level of the above-mentioned corresponding word line is a first level at which corresponding ones of the above-mentioned plurality of memory cells connected to the above-mentioned corresponding wor

Abstract: A semiconductor memory device comprises plural word lines including one or more redundant word lines, plural pairs of bit lines, plural memory cells connected to the plural word lines and the plural pairs of bit lines, plural word-line drivers which are connected to one ends of the plural word lines and controlled by plural word-line control signals respectively, and plural word-line control elements which are connected to other ends of the plural word lines and controlled by a control signal activated at the precharge of the bit lines.

Abstract: A semiconductor memory includes a memory cell array, a redundancy repair signal generator, and a row decoder. The memory cell array includes a plurality of memory cell rows and at least one redundant memory cell row. The redundancy repair signal generator generates a redundancy repair signal that indicates an address of a defective memory cell row. The row decoder receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the redundant memory cell row in accordance with the redundancy repair signal generated by the redundancy repair signal generator. The redundancy repair signal generator is located opposite to the row decoder with the memory cell array placed therebetween. This configuration can achieve a reduction in free space and thus a reduction in area loss.

Abstract: A semiconductor memory device comprises plural word lines including one or more redundant word lines, plural pairs of bit lines, plural memory cells connected to the plural word lines and the plural pairs of bit lines, plural word-line drivers which are connected to one ends of the plural word lines and controlled by plural word-line control signals respectively, and plural word-line control elements which are connected to other ends of the plural word lines and controlled by a control signal activated at the precharge of the bit lines.

Abstract: A semiconductor integrated circuit including an internal voltage step down circuit exhibits a first voltage characteristic I having substantially no dependence on an external power supply voltage VEXT and holding an internal power supply voltage VINT at a constant voltage VA if the external power supply voltage VEXT is in the range between two predetermined values V1 and V2. On and after the external power supply voltage VEXT exceeds the predetermined value V2, the circuit exhibits a second voltage characteristic II, in which the internal power supply voltage VINT varies from the constant voltage VA in accordance with the external power supply voltage VEXT, during a non-accelerated test (operation margin certification test). On the other hand, during the accelerated test, the circuit exhibits a third voltage characteristic III in which the internal power supply voltage VINT reaches a certain voltage VB (>VA) and goes on increasing from VB in accordance with the external power supply voltage VEXT.