Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

Abstract: In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t?r?35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 ?m to 30 ?m and larger than that of the second curved surface.

Abstract: A probe card has a tip portion of a probe needle having a flat shape and an area of 78.5 ?m2 or larger. The probe card also has load setting means for setting a load to the tip portion to be 80 kgf/mm2 or lower when the tip portion is pressed against an electrode pad, and intersection angle setting means for setting an intersection angle of a plane of the electrode pad with a plane of the tip portion to be 2° or smaller when the tip portion is pressed against the electrode pad. With this, a probe card that decreases damage to an electrode pad and an interlayer insulation film of a lower layer, suppresses generation of a crack and enables highly reliable testing of a semiconductor device can be provided.

Abstract: A probe card has an offset substrate electrically connected between a probe card substrate and an interposer substrate with solders. It is possible to secure the thickness of the interposer substrate plus the thickness of the offset substrate for the depth of the positioning holes of the probe needles, which results in the improved positioning accuracy of the probe needle.