Patents by Inventor Yoshinori Deguchi

Yoshinori Deguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6633176
    Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 8t≦r≦23t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 &mgr;m to 30 &mgr;m and larger than that of the second curved surface.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: October 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
  • Patent number: 6628127
    Abstract: A probe card 8 for testing a semiconductor integrated circuit is provided with a plurality of probes for inputting/outputting an electric signal for verifying the operation of a semiconductor integrated circuit 6 to/from bonding pads 7 of the semiconductor integrated circuit. The probes 9 are formed by depositing a conductive film 11 on a surface of a plurality of convex portions formed on a surface of an insulating substrate 10.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: September 30, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Masahiro Tanaka
  • Publication number: 20030057976
    Abstract: A probe card has an offset substrate electrically connected between a probe card substrate and an interposer substrate with solders. It is possible to secure the thickness of the interposer substrate plus the thickness of the offset substrate for the depth of the positioning holes of the probe needles, which results in the improved positioning accuracy of the probe needle.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Deguchi
  • Patent number: 6356096
    Abstract: A test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board includes a first delay element for delaying a signal to be transmitted therethrough for a first signal propagation delay time and a second delay element for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: March 12, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ryoichi Takagi, Masahiro Ueda, Yoshinori Deguchi
  • Publication number: 20020011865
    Abstract: A clock CLK is applied to one input of an MUX 3, while data DATA1 is applied to a delay circuit 2 and to one input of a receiver 6. The delay circuit 2 delays the data DATA1 for a predetermined period of time, and outputs a delay data DDT to the other input of the MUX 3. A test-mode signal STM is applied to a control input of the MUX 3. The MUX 3 is then outputs either the clock CLK or the delay data DDT to respective control inputs of the receiver 6 and a drive 8 on the basis of the test-mode signal STM. The receiver 6 compares the data DATA1 and a reference voltage VREF, and performs buffering on the basis of its comparison result to output an internal signal. Thus, a semiconductor device and a test (DUT) board thereof can achieve a high-precision timing test, irrespective of the timing skew of a tester.
    Type: Application
    Filed: September 3, 1998
    Publication date: January 31, 2002
    Inventors: RYOICHI TAKAGI, MASAHIRO UEDA, YOSHINORI DEGUCHI
  • Publication number: 20010046715
    Abstract: A semiconductor device test probe having a tip portion for being urged against an electrode pad of an integrated semiconductor device to establish an electrical contact against the electrode pad for testing functions of the semiconductor device. The spherical tip portion has a radius of curvature r expressed by 9t≦r≦35t, where r is the radius of curvature of the spherical surface and t is the thickness of the electrode pad. The tip portion may have a first curved surface substantially positioned in the direction of slippage of the probe when the probe is urged against the electrode pad and slipped relative to the electrode pad and a second curved surface opposite to the first curved surface. The first curved surface has a radius of curvature of from 7 &mgr;m to 30 &mgr;m and larger than that of the second curved surface.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 29, 2001
    Inventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Kazunobu Miki
  • Publication number: 20010015650
    Abstract: A probe card 8 for testing a semiconductor integrated circuit is provided with a plurality of probes for inputting/outputting an electric signal for verifying the operation of a semiconductor integrated circuit 6 to/from bonding pads 7 of the semiconductor integrated circuit. The probes 9 are formed by depositing a conductive film 11 on a surface of a plurality of convex portions formed on a surface of an insulating substrate 10.
    Type: Application
    Filed: December 27, 2000
    Publication date: August 23, 2001
    Inventors: Megumi Takemoto, Shigeki Maekawa, Yoshihiro Kashiba, Yoshinori Deguchi, Masahiro Tanaka