Patents by Inventor Yoshinori Fujiwara
Yoshinori Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127901Abstract: Methods, apparatuses, and systems related to masking of self-test results are described. A memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Inventors: Daniel S. Miller, Yoshinori Fujiwara
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Patent number: 11955160Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.Type: GrantFiled: June 22, 2022Date of Patent: April 9, 2024Assignee: Micron Technolgy, Inc.Inventors: Yoshinori Fujiwara, Kevin G. Werhane, Jason M. Johnson, Daniel S. Miller
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Publication number: 20240087625Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Kari Crane, Kevin G. Werhane, Yoshinori Fujiwara, Jason M. Johnson, Takuya Tamano, Daniel S. Miller
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Publication number: 20240071560Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Yoshinori Fujiwara, Takuya Tamano, Jason M. Johnson, Kevin G. Werhane, Daniel S. Miller
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Publication number: 20240071237Abstract: An information processing apparatus includes a controller configured to predict a scattering range of a chemical to be sprayed onto a field by a first unmanned aircraft and control, in a case in which it is determined that the chemical will scatter near the field based on the scattering range, a three-dimensional position or a travel route of a second unmanned aircraft so that downwash of the second unmanned aircraft prevents scattering of the chemical near the field.Type: ApplicationFiled: August 25, 2023Publication date: February 29, 2024Inventors: Ryotaro FUJIWARA, Hirotada NAKANISHI, Fuhito KODAMA, Yuki UCHIDA, Satoshi KOMAMINE, Yoshinori OKADA, Satoshi HIRANO
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Publication number: 20240067339Abstract: A control apparatus includes a controller configured to acquire weather information including a wind speed on a scheduled spraying date and time at which an unmanned aircraft is to spray an agricultural chemical on a field, determine a flight altitude of the unmanned aircraft according to the wind speed, and generate a plan for spraying of the agricultural chemical by the unmanned aircraft, the plan for spraying including the determined flight altitude.Type: ApplicationFiled: August 25, 2023Publication date: February 29, 2024Inventors: Ryotaro FUJIWARA, Hirotada NAKANISHI, Fuhito KODAMA, Yuki UCHIDA, Satoshi KOMAMINE, Yoshinori OKADA, Satoshi HIRANO
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Patent number: 11915775Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.Type: GrantFiled: September 29, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Jack Riley, Scott Smith, Christian Mohr, Gary Howe, Joshua Alzheimer, Yoshinori Fujiwara, Sujeet Ayyapureddi, Randall Rooney
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Publication number: 20240021262Abstract: Methods, apparatuses, and systems related to adjustment of circuit tests are described. A memory device may include a self-test circuit that is configured to selectively suspend collection and/or processing of test results for one or more portions of the self-test.Type: ApplicationFiled: April 20, 2023Publication date: January 18, 2024Inventors: Takuya Tamano, Yoshinori Fujiwara, Daniel S. Miller
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Publication number: 20230420030Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Inventors: Yoshinori Fujiwara, Kevin G. Werhane, Jason M. Johnson, Daniel S. Miller
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Publication number: 20230360718Abstract: Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Takuya Tamano, Yoshinori Fujiwara
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Publication number: 20230343376Abstract: According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.Type: ApplicationFiled: June 15, 2023Publication date: October 26, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Patent number: 11791011Abstract: Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.Type: GrantFiled: May 3, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Takuya Tamano, Yoshinori Fujiwara
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Patent number: 11783909Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.Type: GrantFiled: July 29, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: James S. Rehmeyer, Yoshinori Fujiwara
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Publication number: 20230290428Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for dynamic column select swapping. A memory may have a number of sets of bit lines organized into column planes. If a set of bit lines associated with a first address in a first column plane is defective, it may be repaired by reassigning the first address to a redundant set of bit lines in a global column redundant (GCR) column plane. If a set of bit lines associated with the first address in a second column plane is also defective, then swap logic of the memory may swap the first address to a second address and assign it to the set of bitlines in the second column plane. The second address may then also be repaired by being reassigned to the GCR column plane.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: YOSHINORI FUJIWARA, KRISTOPHER KOPEL, KOSEI KUDO
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Patent number: 11742044Abstract: An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.Type: GrantFiled: August 25, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Yoshinori Fujiwara, Daniel S. Miller
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Patent number: 11727967Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.Type: GrantFiled: January 13, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Patent number: 11705214Abstract: Apparatuses, systems, and methods for self-test mode abort circuit. Memory devices may enter a self-test mode and perform testing operations on the memory array. During the self-test mode, the memory device may ignore external communications. The memory includes an abort circuit which may terminate the self-test mode if it fails to properly finish. For example, the abort circuit may count an amount of time since the self-test mode began and end the self-test mode if that amount of time meets or exceeds a threshold, which may be based off of the expected amount of time for the testing operations to complete.Type: GrantFiled: March 30, 2020Date of Patent: July 18, 2023Assignee: Micron Technologv. Inc.Inventor: Yoshinori Fujiwara
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Publication number: 20230223059Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Patent number: 11670356Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).Type: GrantFiled: July 16, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Yoshinori Fujiwara, Harish V. Gadamsetty, Gary Howe, Dennis G. Montierth, Michael A. Shore, Jason M. Johnson
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Patent number: 11645134Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.Type: GrantFiled: August 20, 2019Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventors: Daniel S. Miller, Kevin G. Werhane, Yoshinori Fujiwara, Christopher G. Wieduwilt, Jason M. Johnson, Minoru Someya