Patents by Inventor Yoshinori Fujiwara

Yoshinori Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190152560
    Abstract: A human-powered vehicle control device includes an electronic controller configured to control a motor that assists in propulsion of a human-powered vehicle in accordance with a human driving force input to the human-powered vehicle. The electronic controller is configured to switch at least five control states imparting different output characteristics to the motor with respect to the human driving force.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 23, 2019
    Inventors: Yoshinori IINO, Keiji TERASHIMA, Takaaki FUJIWARA, Tetsuya KITANI
  • Patent number: 10056154
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9934869
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Publication number: 20180075920
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Application
    Filed: August 3, 2017
    Publication date: March 15, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9824770
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9666307
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9293191
    Abstract: Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Yoshinori Fujiwara
  • Publication number: 20160064065
    Abstract: Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 3, 2016
    Inventors: Yuan He, Yoshinori Fujiwara
  • Patent number: 8736291
    Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Patent number: 8582377
    Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Yoshinori Fujiwara
  • Publication number: 20130254513
    Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 26, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Yoshinori Fujiwara
  • Patent number: 8230274
    Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Publication number: 20120182817
    Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Yoshinori Fujiwara
  • Patent number: 8223583
    Abstract: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by subtracting a value from the row address.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Takumi Nasu, Yoshinori Fujiwara
  • Publication number: 20120120749
    Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Patent number: 8159890
    Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Yoshinori Fujiwara
  • Patent number: 8122304
    Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Publication number: 20110273185
    Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 10, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Patent number: 7990163
    Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Publication number: 20110170365
    Abstract: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2?n number of normal rows and mapping the row address to a redundant row address by subtracting a value from the row address.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Takumi Nasu, Yoshinori Fujiwara