Patents by Inventor Yoshinori Fujiwara

Yoshinori Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6853177
    Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Mari Shibayama, Yoshinori Fujiwara, Yoshihiro Nagura
  • Patent number: 6667915
    Abstract: Redundancy decoders corresponding to a plurality of redundancy circuits, each of which is for relieving a defective memory cell, are classified into a high-priority redundancy decoder used with a higher priority and the other low-priority decoders. When a defective address stored inside is designated as an accessing object, each of the low-priority decoders activates a corresponding redundancy circuit, except for the case where a defective address stored in the high-priority redundancy decoder agrees with an address signal.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: December 23, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Yonezu, Yoshinori Fujiwara
  • Publication number: 20030221144
    Abstract: A defect information storing device includes two tables for storing information on defective points of a semiconductor device. The first table stores column addresses and number of defective points existing on this column address for (r×c+c) lines. The second table stores row addresses, number of defective points existing on this row address, and column identifiers indicating the storage place of the column address of the defective point in the first table for (r×c+r) lines.
    Type: Application
    Filed: October 2, 2002
    Publication date: November 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Shimada, Yoshinori Fujiwara
  • Publication number: 20030210068
    Abstract: An apparatus and a method for testing a semiconductor that can be subjected to the total test in the state of the final product after sealing in the stage of the wafer test in the test of each of a plurality of semiconductor chips sealed together, and can improve the yield of final products. In the assembly step, another chip sealed together with a chip to be measured is mounted on a probe card, and the tester conducts the test of the chip to be measured through a probe needle connected to the chip to be measured. By transmitting a predetermined command, such as writing and/or reading, from a chip to be measured to another chip, the chip to be measured and the other chip are made to execute operations when these chips are sealed together in a package, and the tester is made to analyze the result of operations and to perform pass or fail judgment.
    Type: Application
    Filed: November 15, 2002
    Publication date: November 13, 2003
    Applicants: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Yoshinori Fujiwara, Kazushi Sugiura
  • Publication number: 20030072680
    Abstract: In a colorimetric absorbance measurement apparatus, a filter assembly on which a plurality of filters are arranged in a circular pattern is continuously rotated by a motor at a regular speed based on a motor drive signal fed from a motor drive circuit, each of the filters being characterized by passing only such light components that have wavelengths falling within a range centering on a specific wavelength. The motor drive signal produced by the motor drive circuit is also fed into a timing generator circuit. The timing generator circuit supplies an A/D conversion start signal to an A/D converter in synchronism with the timing at which a selected one of the multiple filters is positioned on the optical axis of a measuring light beam.
    Type: Application
    Filed: September 20, 2002
    Publication date: April 17, 2003
    Inventors: Yasuhiro Higuchi, Yoshinori Fujiwara
  • Publication number: 20030065996
    Abstract: According to the present invention, a pseudo-error signal generating circuit is provided between a memory circuit and a self-test circuit. The pseudo-error signal generating circuit converts an output signal of the memory circuit based on a setting signal to supply a pseudo-error signal necessary to verify the operation of the self-test circuit. The pseudo-error signal generating circuit has a scan chain circuit in which a setting signal is set, and generates a pseudo-error signal based on the setting signal.
    Type: Application
    Filed: April 10, 2002
    Publication date: April 3, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Shimada, Yoshinori Fujiwara
  • Publication number: 20030058716
    Abstract: Redundancy decoders corresponding to a plurality of redundancy circuits, each of which is for relieving a defective memory cell, are classified into a high-priority redundancy decoder used with a higher priority and the other low-priority decoders. When a defective address stored inside is designated as an accessing object, each of the low-priority decoders activates a corresponding redundancy circuit, except for the case where a defective address stored in the high-priority redundancy decoder agrees with an address signal.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 27, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Yonezu, Yoshinori Fujiwara
  • Publication number: 20030017713
    Abstract: A workpiece stage of a resist curing device is devised in which a workpiece on which a resist has been applied is held on a workpiece stage by vacuum suction, in which the workpiece is irradiated with UV radiation with a simultaneous temperature increase, in which it is cooled after UV radiation and by which the resist is cured, the workpiece stage having heating and cooling arrangements, major warping of the carrier is avoided and reliable holding of the workpiece on the carrier surface by vacuum suction obtained by the carrier being made of an aluminum alloy or a copper alloy which meets the following condition:
    Type: Application
    Filed: June 27, 2002
    Publication date: January 23, 2003
    Applicant: Ushiodenki Kabushiki Kaisha
    Inventors: Yoshinori Fujiwara, Yasuhiko Kenjo, Yoshihiko Watanabe
  • Publication number: 20020153525
    Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 24, 2002
    Inventors: Mari Shibayama, Yoshinori Fujiwara, Yoshihiro Nagura
  • Patent number: 5776395
    Abstract: This details a production method for a blade for electrophotographic devices, made of thermosetting type polyurethane, including the steps of mixing and stirring the liquid polyurethane prepolymer which is a raw material component for a thermosetting type polyurethane polymer and the liquid crosslinking agent, discharging the mixture thereof into a die having a concave cross section in a molding drum, heating it via an endless belt which is in contact with the outer peripheral face of the molding drum and runs with the rotation of the drum 20 to continuously mold a banded blade molding S having a prescribed width, and cutting the blade molding to a prescribed length after cooling it down.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: July 7, 1998
    Assignee: Bando Kagaku Kabushiki Kaisha
    Inventors: Yoshinori Fujiwara, Takeshi Noda, Yuichi Shigechika, Toshiharu Taniguchi, Arata Tani
  • Patent number: 5611149
    Abstract: A weld gage includes a gage body having a front gage plate and a back gage plate disposed in parallel facing relation to the front gage plate with a gap formed therebetween. The front gage plate has at least one kind of metric graduations provided at prescribed positions on an outer surface thereof, whereas the back gage plate has inch graduations at positions corresponding to the positions of the metric graduations of the front gage plate on an outer surface thereof. A slide scale is disposed between the front gage plate and the back gage plate for sliding movement. An angle-measuring plate is pivotally disposed between the front gage plate and the back gage plate.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: March 18, 1997
    Assignee: Fuji Tool Co., Ltd.
    Inventor: Yoshinori Fujiwara