Patents by Inventor Yoshinori Imamura
Yoshinori Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9266379Abstract: A thermochromic writing instrument contains a thermochromic ink, wherein a writing body is accommodated in a barrel movably in a longitudinal direction, an operation portion is provided on the outer surface of the barrel, a pen tip of the writing body is constituted so as to be projectable/retractable from/into a front-end hole of the barrel by operating the operation portion, the thermochromic ink is contained in the inside of the writing body, the pen tip capable of ejecting the thermochromic ink is provided at the front end of the writing tool, and a friction portion capable of thermally changing the color of the handwriting of the thermochromic ink by the frictional heat generated when the handwriting is rubbed with the friction portion is provided on the outer surface of the barrel.Type: GrantFiled: November 1, 2012Date of Patent: February 23, 2016Assignees: THE PILOT INK CO., LTD., KABUSHIKI KAISHA PILOT CORPORATIONInventors: Yoshinori Imamura, Nobuo Sekine, Masashi Ando
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Patent number: 9233574Abstract: A thermochromic writing instrument contains a thermochromic ink, wherein a writing body is accommodated in a barrel movably in a longitudinal direction, an operation portion is provided on the outer surface of the barrel, a pen tip of the writing body is constituted so as to be projectable/retractable from/into a front-end hole of the barrel by operating the operation portion, the thermochromic ink is contained in the inside of the writing body, the pen tip capable of ejecting the thermochromic ink is provided at the front end of the writing tool, and a friction portion capable of thermally changing the color of the handwriting of the thermochromic ink by the frictional heat generated when the handwriting is rubbed with the friction portion is provided on the outer surface of the barrel.Type: GrantFiled: November 1, 2012Date of Patent: January 12, 2016Assignees: THE PILOT INK CO., LTD., KABUSHIKI KAISHA PILOT CORPORATIONInventors: Yoshinori Imamura, Nobuo Sekine, Masashi Ando
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Publication number: 20130121744Abstract: A thermochromic writing instrument contains a thermochromic ink, wherein a writing body is accommodated in a barrel movably in a longitudinal direction, an operation portion is provided on the outer surface of the barrel, a pen tip of the writing body is constituted so as to be projectable/retractable from/into a front-end hole of the barrel by operating the operation portion, the thermochromic ink is contained in the inside of the writing body, the pen tip capable of ejecting the thermochromic ink is provided at the front end of the writing tool, and a friction portion capable of thermally changing the color of the handwriting of the thermochromic ink by the frictional heat generated when the handwriting is rubbed with the friction portion is provided on the outer surface of the barrel.Type: ApplicationFiled: November 1, 2012Publication date: May 16, 2013Inventors: Yoshinori IMAMURA, Nobuo SEKINE, Masashi ANDO
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Patent number: 8322937Abstract: A thermochromic writing instrument contains a thermochromic ink, wherein a writing body 8 is accommodated in a barrel 2 movably in a longitudinal direction, an operation portion 5 is provided on the outer surface of the barrel 2, and a pen tip 81 of the writing body 8 is constituted so as to be projectable/retractable from/into a front-end hole 31 of the barrel 2 by operating the operation portion 5. The thermochromic ink 83 is contained in the inside of the writing body 8, the pen tip 81 capable of ejecting the thermochromic ink 83 is provided at the front end of the writing tool, and a friction portion 4 capable of thermally changing the color of the handwriting of the thermochromic ink 83 by the frictional heat generated when the handwriting is rubbed with the friction portion 4 is provided on the outer surface of the barrel 2.Type: GrantFiled: February 8, 2008Date of Patent: December 4, 2012Assignee: The Pilot Ink Co., Ltd.Inventors: Yoshinori Imamura, Nobuo Sekine, Masashi Ando
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Patent number: 7723753Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: GrantFiled: December 21, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kenji Sasaki, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Publication number: 20100098476Abstract: There is provided a thermochromic writing instrument containing a thermochromic ink, which is capable of easily changing color of the handwriting of thermochromic ink by rubbing and also being quickly brought into a writing-capable state (pen-tip-projected state) or a stored state (pen-tip-retracted state) even when the user can use only one hand.Type: ApplicationFiled: February 8, 2008Publication date: April 22, 2010Applicant: THE PILOT INK CO., LTD.Inventors: Yoshinori Imamura, Nobuo Sekine, Masashi Ando
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Publication number: 20090194792Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.Type: ApplicationFiled: March 27, 2009Publication date: August 6, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Satoru Konishi, Tsuneo Endo, Hirokazu Nakajima, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura, Atsushi Kurokawa
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Patent number: 7563021Abstract: There are provided a process and the like for judging a residual lifetime of a run-flat tire and an end stage of the residual lifetime thereof during continuous running at a run-flat state.Type: GrantFiled: August 12, 2003Date of Patent: July 21, 2009Assignee: Bridgestone CorporationInventors: Eiji Ichihara, Yoshinori Imamura, Takehiko Yamada
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Patent number: 7511315Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.Type: GrantFiled: April 19, 2005Date of Patent: March 31, 2009Assignee: Renesas Technology Corp.Inventors: Satoru Konishi, Tsuneo Endo, Hirokazu Nakajima, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura, Atsushi Kurokawa
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Publication number: 20080224174Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: ApplicationFiled: December 21, 2007Publication date: September 18, 2008Inventors: Kenji SASAKI, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Patent number: 7411487Abstract: A tire-information administration system includes a plurality of sensor modules installed in tires; at least one reception module configured to receive data from the sensor modules; and a central control module configured to command the reception module to acquire data from the sensor modules. The central control module includes a predetermined number of connection ports for the reception module, assigned in advance to each sensor modules; and a specifically configured control means.Type: GrantFiled: January 20, 2004Date of Patent: August 12, 2008Assignee: Bridgestone CorporationInventors: Koji Takao, Tatehiko Yamada, Yoshinori Imamura
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Patent number: 7378690Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: GrantFiled: March 26, 2007Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20070257332Abstract: A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film for masking thereby to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront, and the increase of resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.Type: ApplicationFiled: July 10, 2007Publication date: November 8, 2007Inventors: Atsushi KUROKAWA, Masao Yamane, Yoshinori Imamura
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Patent number: 7256433Abstract: A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.Type: GrantFiled: April 28, 2004Date of Patent: August 14, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Masao Yamane, Yoshinori Imamura
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Publication number: 20070176207Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: ApplicationFiled: March 26, 2007Publication date: August 2, 2007Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Patent number: 7214558Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: GrantFiled: October 25, 2005Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20070059853Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: October 31, 2006Publication date: March 15, 2007Inventors: Atsushi KUROKAWA, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Patent number: 7132320Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: November 4, 2005Date of Patent: November 7, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Publication number: 20060139157Abstract: A tire-information administration system includes a plurality of sensor modules installed in tires; at least one reception module configured to receive data from the sensor modules; and a central control module configured to command the reception module to acquire data from the sensor modules. The central control module includes a predetermined number of connection ports for the reception module, assigned in advance to each sensor modules; and a specifically configured control means.Type: ApplicationFiled: January 20, 2004Publication date: June 29, 2006Inventors: Koji Takao, Tatehiko Yamada, Yoshinori Imamura
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Publication number: 20060138459Abstract: Provided is a semiconductor device equipped with HBTs capable of satisfying both thermal stability and reliability and having improved electrostatic breakdown voltage. The HBT according to the present invention is obtained by successively forming, over the main surface of a substrate made of a compound semiconductor, a sub-collector layer, a collector layer, a base layer, an emitter layer, a collector electrode electrically connected to the collector layer, a base electrode electrically connected to the base layer, an emitter mesa layer formed over the emitter layer and electrically connected to the emitter layer, and an emitter electrode electrically connected to the emitter mesa layer. The emitter mesa layer has a semiconductor layer made of an n type GaAs layer, a high concentration semiconductor layer made of an n+ type GaAs layer over the semiconductor layer and a ballast resistor layer made of an n type InGaAs layer over the high concentration semiconductor layer.Type: ApplicationFiled: December 27, 2005Publication date: June 29, 2006Inventors: Atsushi Kurokawa, Isao Ohbu, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura