Patents by Inventor Yoshinori Imamura
Yoshinori Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20060093015Abstract: There are provided a process and the like for judging a residual lifetime of a run-flat tire and an end stage of the residual lifetime thereof during continuous running at a run-flat state.Type: ApplicationFiled: August 12, 2003Publication date: May 4, 2006Inventors: Eiji Ichihara, Yoshinori Imamura, Takehiko Yamada
-
Patent number: 7029938Abstract: Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of gold germanium, nickel and Au in this order over the entire surface of a substrate, so that the resulting stacked film will not become an isolated pattern. Thus, the stacked film over the base mesa is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa. Generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material which hardly reacts with an n-type GaAs layer or n-type InGaAs layer.Type: GrantFiled: March 26, 2004Date of Patent: April 18, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
-
Publication number: 20060057789Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: November 4, 2005Publication date: March 16, 2006Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20060032762Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: ApplicationFiled: October 25, 2005Publication date: February 16, 2006Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
-
Patent number: 6989301Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: September 30, 2003Date of Patent: January 24, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20050258452Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.Type: ApplicationFiled: April 19, 2005Publication date: November 24, 2005Inventors: Satoru Konishi, Tsuneo Endo, Hirokazu Nakajima, Yasunari Umemoto, Satoshi Sasaki, Chushiro Kusano, Yoshinori Imamura, Atsushi Kurokawa
-
Patent number: 6931912Abstract: A method for directly and accurately estimating friction coefficient of a road surface independently from the slip rate is disclosed. The method measures tangential and vertical forces acting on an elastic body 3 of an elastic wheel 1, and calculates the friction coefficient of a road surface based on the measured values of these forces and angular rate of the wheel 1.Type: GrantFiled: June 21, 2002Date of Patent: August 23, 2005Assignee: Bridgestone CorporationInventors: Shuhei Tsuchie, Yoshinori Imamura, Koji Takao, Masanobu Toyofuku
-
Patent number: 6867079Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: September 30, 2003Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20040212044Abstract: A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.Type: ApplicationFiled: April 28, 2004Publication date: October 28, 2004Inventors: Atsushi Kurokawa, Masao Yamane, Yoshinori Imamura
-
Publication number: 20040188707Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: ApplicationFiled: March 26, 2004Publication date: September 30, 2004Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
-
Publication number: 20040163454Abstract: A method for directly and accurately estimating friction coefficient of a road surface independently from the slip rate is disclosed. The method measures tangential and vertical forces acting on an elastic body 3 of an elastic wheel 1, and calculates the friction coefficient of a road surface based on the measured values of these forces and angular rate of the wheel 1.Type: ApplicationFiled: January 16, 2004Publication date: August 26, 2004Inventors: Shuhei Tsuchie, Yoshinori Imamura, Koji Takao, Masanobu Toyofuku
-
Patent number: 6724020Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: April 23, 2003Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
-
Publication number: 20040063259Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: September 30, 2003Publication date: April 1, 2004Applicant: Hitachi, Ltd.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20040063292Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: September 30, 2003Publication date: April 1, 2004Applicant: Hitachi, Ltd.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20040021458Abstract: A displacement sensor comprising a board-like magnet 20 mounted on an object 10 to be measured and magnetized in a thickness direction, a first Hall element 21, arranged opposite near the center of the pole face 20a as an XY plane of the magnet 20, for detecting a component parallel to the Z axial direction which is the thickness direction of the magnet 20 of a magnetic field from the magnet 20, and a second Hall element 22, arranged on a side opposite to the magnet 20 of the first Hall element 21, for detecting a component parallel to the X axial direction of the magnetic field from the magnet 20 so that it can detect displacements in two axial directions (X axis and Y axis) of the object 10 to be measured at the same time efficiently and accurately.Type: ApplicationFiled: May 19, 2003Publication date: February 5, 2004Inventor: Yoshinori Imamura
-
Patent number: 6649458Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: January 22, 2003Date of Patent: November 18, 2003Assignee: Hitachi, Ltd.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Publication number: 20030205719Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: ApplicationFiled: April 23, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
-
Publication number: 20030157775Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: January 22, 2003Publication date: August 21, 2003Applicant: Hitachi, Ltd.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
-
Patent number: 6576937Abstract: A semiconductor device including a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: May 24, 2001Date of Patent: June 10, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
-
Publication number: 20020005525Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: ApplicationFiled: May 24, 2001Publication date: January 17, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura