Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Abstract: Provided are an inspection method, a program, and an inspection system capable of improving accuracy of inspecting a color of a surface of an object. The inspection method includes acquisition step and comparison step. Acquisition step is a step of acquiring a target image of a surface of an object obtained by an imaging system imaging the surface of the object illuminated by an illumination system. Comparison step, is a step of comparing a color of an attention region on the target image with a color of a reference region. The reference region is a region of a reference image of a surface of a reference object as a reference of a color of the object, and a region corresponding to a combination of an incident angle of light from the illumination system and a reflection angle of light to the imaging system in the attention region.

Abstract: A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. In some examples, the internal data clock signals may be generated from a system clock signal responsive to a data clock signal. In some examples, the internal data clock signal may be generated by sampling the system clock signal. In some examples, the sampling may be performed responsive to the data clock signal. In some examples, a latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.

Abstract: Provided are an inspection method, a program, and an inspection system capable of improving accuracy of inspecting a color of a surface of an object. The inspection method includes acquisition step and comparison step. Acquisition step is a step of acquiring a target image of a surface of an object obtained by an imaging system imaging the surface of the object illuminated by an illumination system. Comparison step is a step of comparing a color of an attention region on the target image with a color of a reference region. The reference region is a region of a reference image of a surface of a reference object as a reference of a color of the object, and a region corresponding to a combination of an incident angle of light from the illumination system and a reflection angle of light to the imaging system in the attention region.

Abstract: An object is to simply and easily evaluate differences in behavior of the eyes of subjects. A binocular measurement system 1 includes a photodetector 7 that detects reflected light from the right eye ER and the left eye EL of a subject, and outputs image signal of the reflected light, a feature amount calculating unit 11 that calculates a feature amount corresponding to the right eye ER and a feature amount corresponding to the left eye EL based on the image signal, and a comparison value calculating unit 13 that calculates, based on the two feature amounts, a comparison value obtained by comparing the two feature amounts.

Abstract: A learning assistance device for a user to perform a learning task includes: a first concentration level estimator that estimates a first concentration level of the user, by analyzing information from an image capturing section that captures an image of a user; a second concentration level estimator that estimates a second concentration level of the user, by analyzing information which the user has actively input when performing a learning task; and a presentation switching section that switches between learning task content and between presentation schemes, based on at least one of the first concentration level or the second concentration level.

Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

Abstract: A plurality of pixels are arranged two-dimensionally in a matrix and individually include a first photosensitive portion and a second photosensitive portion. A plurality of first wirings connect a plurality of first photosensitive portions to each other for every row. A plurality of second wirings connect a plurality of second photosensitive portions to each other for every column. A first reading unit 21 is arranged to read signal data through at least some of the plurality of first wirings. A second reading unit 31 is arranged to read signal data through at least some of the plurality of second wirings. The first reading unit 21 has a reading pixel setting unit 26 arranged to set, based on signal data read in the first frame, a pixel group for reading signal data in a second frame subsequent to a first frame from the plurality of pixels.

Abstract: A positive resist composition is provided comprising two onium salts, a base polymer comprising acid labile group-containing recurring units, and an organic solvent. The positive resist composition forms a pattern having PED stability and improved properties including DOF, LWR, and controlled footing profile.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: An epoxy compound of formula (1) is provided. A resist composition comprising the epoxy compound is capable of adequately controlling the diffusion length of acid generated from an acid generator without sacrificing sensitivity.

Abstract: Provided are an inspection method, a program, and an inspection system capable of improving accuracy of inspecting a color of a surface of an object. The inspection method includes acquisition step and comparison step. Acquisition step is a step of acquiring a target image of a surface of an object obtained by an imaging system imaging the surface of the object illuminated by an illumination system. Comparison step is a step of comparing a color of an attention region on the target image with a color of a reference region. The reference region is a region of a reference image of a surface of a reference object as a reference of a color of the object, and a region corresponding to a combination of an incident angle of light from the illumination system and a reflection angle of light to the imaging system in the attention region.

Abstract: A plurality of pixels are arranged two-dimensionally in a matrix and individually include a first photosensitive portion and a second photosensitive portion. A plurality of first wirings connect a plurality of first photosensitive portions to each other for every row. A plurality of second wirings connect a plurality of second photosensitive portions to each other for every column. A first reading unit 21 is arranged to read signal data through at least some of the plurality of first wirings. A second reading unit 31 is arranged to read signal data through at least some of the plurality of second wirings. The first reading unit 21 has a reading pixel setting unit 26 arranged to set, based on signal data read in the first frame, a pixel group for reading signal data in a second frame subsequent to a first frame from the plurality of pixels.

Abstract: A mounted object detection device includes: a load sensor in which a plurality of sensor parts each configured to detect a load are disposed in a matrix shape; and a controller configured to detect a situation of a mounted object on the load sensor on the basis of an output from the load sensor. The controller: detects a load distribution on a detection region of the load sensor on the basis of an output from the load sensor; discerns which of a person or animal and a thing the mounted object is, on the basis of the load distribution; and when having discerned that the mounted object is a thing, discerns whether or not a person or an animal is mounted on the thing, on the basis of temporal change in the load distribution.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A light detection device detects an incident position of light. The plurality of pixels are arranged two-dimensionally in a matrix and individually have a first photosensitive portion and a second photosensitive portion. The first circuit connects a plurality of first photosensitive portions to each other for every row. The second circuit connects a plurality of second photosensitive portions to each other for every column. The first reading unit reads signal data through the first circuit. The second reading unit reads signal data through the second circuit. The first circuit includes row switches arranged to switch electrical connection and disconnection between first photosensitive portions adjacent to each other in the same row.

Abstract: A plurality of pixels are arranged two-dimensionally in a matrix and individually include a first photosensitive portion and a second photosensitive portion. A plurality of first wirings connect a plurality of first photosensitive portions to each other for every row. A plurality of second wirings connect a plurality of second photosensitive portions to each other for every column. A first reading unit is arranged to read signal data through at least some of the plurality of first wirings. A second reading unit is arranged to read signal data through at least some of the plurality of second wirings. The first reading unit has a reading pixel setting unit arranged to set, based on signal data read in the first frame, a pixel group for reading signal data in a second frame subsequent to a first frame from the plurality of pixels.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Abstract: Provided is a position detection sensor. In a first pixel part, as an incident position is closer to a first end of a first pixel pair group in a second direction, an intensity of a first electric signal decreases. In a second pixel part, as the incident position is closer to the first end, an intensity of a second electric signal increases. In a third pixel part, as the incident position is closer to a second end of a second pixel pair group in a first direction, an intensity of a third electric signal decreases. In a fourth pixel part, as the incident position is closer to the second end, an intensity of a fourth electric signal increases. A calculation unit calculates a second position on the basis of the first and second electric signals, and calculates a first position on the basis of the third and fourth electric signals.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.