Abstract: Disclosed herein is a semiconductor device that includes a clock terminal supplied with a first clock signal from outside; a dividing circuit dividing a frequency of the first clock signal to generate a plurality of second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal, the multiplexer having a predetermined operating delay time; a data strobe terminal supplied with a first data strobe signal from outside; a strobe signal generation circuit adding the predetermined operating delay time to the first data strobe signal to generate a second data strobe signal; and a skew detection circuit measuring a skew between the third clock signal and the second data strobe signal.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A semiconductor device includes an internal circuit and an internal voltage generation circuit which generates an internal voltage stabilized with respect to a variation of the power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The internal voltage generation circuit performs control so that when the power supply voltage rises to exceed a predetermined value, an operation of stabilizing the internal voltage is stopped to cause the internal voltage to increase with the rise of the power supply voltage.

Abstract: A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: To cancel a delay time that occurs in a delay circuit due to temperature and voltage changes. The delay circuit includes a plurality of first and second inverters that are each composed of an N-channel first transistor and a P-channel second transistor connected in series, and P-channel third transistors that are connected between a first power supply wiring and the input nodes of the second inverters. According to the present invention, the presence of the third transistors cancels characteristic variations of the second transistors included in the respective plurality of inverters even if there are changes in temperature, voltage, etc. Consequently, when temperature, voltage, or the like changes, variations in the amount of delay of the entire delay circuit can be regarded as resulting from characteristic variations of the first transistors.

Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.

Abstract: A computer system in an embodiment comprises a storage apparatus, a host computer, and a copy control program. The storage apparatus performs copy operations of volumes allocated to a guest OS of the host computer. The copy control program obtains volume information of the guest OS from a VM control program at a given time. The control program compares the information with previous volume information of the guest OS and performs volume copy control for the guest OS in accordance with the comparison result. This process achieve appropriate copy operations even if the association relationship between the guest OS and volumes is changed during system operation.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: In an aspect of the invention, a primary storage system (P system) manages write times of write data of one or more primary volumes (P volumes). The P system sequentially sends journals including write data of the P volumes and values indicating order of writing the write data of the P volumes to the secondary storage system (S system). The S system sequentially stores the write data in the journals from the P system to one or more secondary volumes (S volumes) according to the values. The S system sends identification information on the latest write data of the S volumes to the P system. The P system sends a management system information to indicate the latency between the write time of the data identified with the identification information and the write time of the latest data of the P volumes at the time of receipt of the identification information.

Abstract: To include a switch transistor inserted between a data bus and an input end of a signal receiving circuit and turned off when a potential of the data bus reaches VPERI?NVth, and an assist transistor that drives the input end of the signal receiving circuit to have VPERI. According to the present invention, because the switch transistor and the assist transistor assist a receiving operation performed by the signal receiving circuit, amplitude of a transferred signal can be reduced without reducing a transfer rate. With this configuration, power consumed by charging or discharging of the data bus can be reduced.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus 4 connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes a plurality of external input/output buffers 23, and a plurality of bus interface circuits 24. The plurality of bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers.

Abstract: A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder.

Abstract: The present invention provided a content delivery system that can deliver content by way of the Internet. In the system, a browser requests a content server to deliver a startup file. The content server transmits the startup file to the browser. The startup file describes that the content is to be delivered by streaming or that it is to be delivered by downloaded files. A content reproducing section determines if the content is that to be delivered by streaming or that to be delivered by downloaded files according to the description of the startup file it receives from the browser. A television receiving set may be used as content processing apparatus for receiving the delivery of the content from a content delivery apparatus of such a system.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.