Abstract: In a data transmission method of the present invention, not only when relay of input packets is performed but also transmission of a retransmission packet or a correction packet is performed, changes in an output rate due to output rate control is suppressed, and data transmission is efficiently performed according to a capacity of an output channel. A data transmission device comprises a packet priority decision unit 15 for deciding priorities of input packets, a retransmission packet, and an FEC packet, an output delay calculation unit 17 for calculating a delay time until data of the respective packets is reproduced by a receiving terminal, and an FEC packet generation unit 19 for generating an FEC packet containing an error correcting code which corresponds to a packet designated on the basis of the priorities of the respective packets.

Abstract: A data transmission apparatus for relaying data transmitted from the transmitting end in units of packets, each packet having additional information relating to its sequence number, priority and data reproduction time, comprises: a receiving unit for receiving packets transmitted from the transmitting end; a priority decision unit for deciding the priority of each of the received packets; a retransmission packet storage unit for storing packets the priorities of which are equal to or higher than a predetermined value, as retransmission packets, on the basis of the priority of each packet decided by the priority decision unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit for deciding whether retransmission of the packet for which the retransmission request has been made should be performed or not, on the basis of the retransmission request and the storage status of the retransmission packets in the retran

Abstract: Provided is a content classifying section 203 for classifying and bundling to-be-transmitted contents on the basis of any piece of information of media kind, IP address, port number and session identifier. A packet header compressing section 204 carries out header compression on the transmission packet. Due to this, because contents can be packet-transferred with efficiency and excellent error resistance by the use of a communication and broadcast network, it is possible to realize, even on the Internet for broadcast in a broadcast form, a quality broadcast free of image or sound discontinuity as the terrestrial-wave TV broadcast.

Abstract: The present invention correctly decodes data encoded with a variable-length encoding method that improves the compression ratio. The variable-length encoding method encodes a unit data composed of a plurality of sub-data while referencing parameter tables, and includes the following steps: an initialization step in which an obtained parameter table is set to initial values; a parameter table information encoding step in which information related to the initialized parameter table is encoded; a parameter obtainment step in which encoding parameters to be used in the encoding of sub-data are obtained from the parameter table; a sub-data encoding step in which variable-length encoding of the sub-data is performed with reference to the obtained encoding parameters, and an encoded information placement step in which the encoded information is placed in a position in which the information can be obtained before the encoded unit data.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip.

Abstract: The moving picture data reproducing device 200 is comprised of file inputting unit 201 for acquiring an MP4 file, data file temporary storage unit 202 that has an area for temporarily storing the accepted input MP4 file, data file analyzing unit 203 for analyzing the file header information by reading the input MP4 file, data decoding unit 204 for reading entity data from data file temporary storage unit 202 based on the analysis result of data file analyzing unit 203 and decoding the entity data, data reproducing unit 205 for reproducing the decoded entity data and outputting the entity data to a displaying device, RA information table generating unit 206 for transforming random access information generated based on the analysis result of data file analyzing unit 203 into a table, file outputting unit 207 for outputting a new MP4 file by integrating the RA information table and the input-completed MP4 file, and file storing unit 208 for storing the outputted MP4 file.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A data transmission apparatus for relaying data transmitted from the transmitting end in units of packets, each packet having additional information relating to its sequence number, priority and data reproduction time, comprises: a receiving unit for receiving packets transmitted from the transmitting end; a priority decision unit for deciding the priority of each of the received packets; a retransmission packet storage unit for storing packets the priorities of which are equal to or higher than a predetermined value, as retransmission packets, on the basis of the priority of each packet decided by the priority decision unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit for deciding whether retransmission of the packet for which the retransmission request has been made should be performed or not, on the basis of the retransmission request and the storage status of the retransmission packets in the retran

Abstract: A semiconductor intergrated circuit device is comprised a main portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: A semiconductor integrated circuit device includes a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit. A sense amplifier unit control circuit electrically disconnects sense amplifier circuits from the main memory and data is transferred from the main memory to the auxiliary memory in this disconnected state. A data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to the main memory unit.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: A memory system and a control method for the same enable stable operation at high frequencies without a radiant noise problem. In the memory system, a plurality of DRAMs is provided on each of a plurality of modules, and each DRAM is connected with a memory controller by data lines and clock lines. The clock lines have a topology exclusively applied to each module, while the data lines have a topology for connecting them to their associated DRAMs on each module. Command/address lines also have a topology similar to that of the clock lines. In this case, data signals supplied through the data lines and clock and command/address signals supplied through the clock lines and the command/address lines are transferred at different timings between the DRAMs and the memory controller. For this reason, the DRAMs and the memory controller are provided with circuits for matching the timings.

Abstract: A data transmission apparatus for relaying data transmitted from the transmitting end in units of packets, each packet having additional information relating to its sequence number, priority, and data reproduction time, comprises: a receiving unit for receiving packets transmitted from the transmitting end; a priority decision unit for deciding the priority of each of the received packets; a retransmission packet storage unit for storing packets the priorities of which are equal to or higher than a predetermined value, as retransmission packets, on the basis of the priority of each packet decided by the priority decision unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit for deciding whether retransmission of the packet for which the retransmission request has been made should be performed or not, on the basis of the retransmission request and the storage status of the retransmission packets in the retra

Abstract: A video image decoding and composing apparatus includes: a composing information memory for storing composition information; an arbitrary shape object decoding means for decoding a coded signal of an arbitrary shape object video image; a shape memory for storing a shape signal which is decoded by the arbitrary shape object decoding means; a texture memory for storing a texture signal which is decoded by the arbitrary shape object decoding means; a rectangular shape object decoding means for decoding a coded signal of a rectangular shape object video image; a video image memory for storing a video image signal which is decoded by the rectangular shape object decoding means; a composing means for composing the shape signal stored in the shape memory, the texture signal stored in the texture memory, and the video image signal stored in the video image memory, in accordance with the composition information stored in the composition information memory; a position indicating means for indicating a position in the c

Abstract: A data reproduction apparatus includes a reception unit for receiving coded data of multimedia data, a decoding unit for decoding the received coded data, and a video/audio output unit for performing image display or audio output on the basis of the decoded multimedia data, and the operation of at least one of the reception unit, the decoding unit, and the video/audio output unit is restricted according to the data structure of the inputted coded multimedia data and user setting so as to reduce consumption of battery power by the respective units.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: A data transmission system comprises a data transmission apparatus for transmitting plural pieces of object data for reproducing plural objects constituting a scene, and a data receiving apparatus for receiving the plural pieces of object data and reproducing the scene on the basis of the object data. The data transmission apparatus comprises a first transmission unit for transmitting first object data, amongst the plural pieces of object data, such that reproduction of the scene is performed at the receiving end on the basis of the first object data after the transmission of the first object data has been completed, and a second transmission unit for transmitting second object data other than the first object data, amongst the plural pieces of object data, such that reproduction of the scene is performed at the receiving end on the basis of the second object data during the transmission of the second object data.

Abstract: A file creating device 201 includes (1) a data input unit 202 that receives audio data from outside and outputs digital audio data, (2) an encoding unit 203 that encodes the digital audio data, creates one access unit by putting together encoded samples so as to keep the size of all the access units same in a byte unit, and outputs the access units to a file output unit 205, (3) a format creating unit 204 that acquires format information from the encoding unit 203, creates header information of an MP4 file, and outputs the header information to the file output unit 205, and (4) the file output unit 205 that creates an access unit train by multiplexing the access units acquired from the encoding unit 203, and outputs the MP4 file by combining the access unit train and the header information acquired from the format creating unit 204.

Abstract: The image output apparatus comprises first and second decoders 11a and 11b for decoding encoded object data E1 and W2 corresponding to the first and second objects, video data composition means 12 for compositing output data of these decoders frame by frame according to a predetermined composition period, a buffer 13 for storing composite data of a predetermined number of frames from the buffer 13 and image output apparatus 14 for reading the composite data from the buffer 13 and outputting the composite data, wherein according to a result of comparison between scheduled display time T determined by processing ability of the apparatus and set display time Tout when the composite data stored in the buffer is to be displayed, video data composition period of the video data composition means 12 is determined.