Abstract: A remote copy system comprises a primary storage system having a primary volume, and a secondary storage system having a secondary volume forming a pair relationship with the primary volume. When the primary storage system receives a write command from a primary host computer, it stores the command in the primary volume and creates a journal added with time information. The secondary storage system receives the journal from the primary storage system and updates the secondary volume based on the received journal. The primary host computer determines, based on the operating status of the secondary storage system, either the time added to the latest journal that the secondary storage system received or the time added to the latest journal that updated the secondary volume as the recovery point objective, and provides the determined time this to the user.

Abstract: A multiplex scheme conversion apparatus (103) includes (i) a packet loss judgment unit (202) that judges the packet loss of a TS packet, performs error processing in the case where a packet loss is detected, and outputs the payload data on which error processing has already been performed and (ii) a Box making unit (206) that makes ‘moov’ including error information and ‘mdat’ based on inputted AU data and the display time in a PES header.

Abstract: A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresses of first and second memory cell arrays of the plurality of memory cell arrays. The first internal address may designate a first area of the first memory cell array. The second internal address may designate a second area of the second memory cell array. The controller reads a series of data from the first area sequentially and writes the series of read data into the second area sequentially without transferring the series of read data to the plurality of ports.

Abstract: The multiplexer includes a first input unit, a second input unit, a first analysis unit, and a second analysis unit. Moreover, the multiplexer includes a packetization part determination unit that determines the packetization part of audio data in a way that the packetization part is made to be the same or approximately the same as a playback start time of a video sample that is placed in a leading part of the packetization part of video data after determining the packetization part of the video data based on video sample header information. Furthermore, the multiplexer includes a packet header part generation unit that generates a packet header part on the basis of the determined packetization part, a packet data generation unit that generates a packet data unit on the basis of the determined packetization part and a packet connection unit that generates a packet.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for each of the configured second groups, and the acquired journals are reflected in the corresponding second volume in the corresponding second group. In addition, the latest time stamp of each of the second groups containing the journals retained in the second volume in an unreflected state is compared, the time difference of the latest and oldest time stamps is detected, and prescribed control processing is executed for acquiring the journals regarding the second group with the oldest time stamp in preference to the journals regarding other second groups when the time difference exceeds a preset threshold value.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

Abstract: A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

Abstract: A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output circuits of the signal terminals; test-purpose signal terminals fewer than the signal terminals; a selection portion which, as data to be written to the memory cells, selects data input from the signal terminals or data input from the test-purpose signal terminals, and repetitively allocates inputs of the test-purpose signal terminals to inputs of the signal terminals based on an arrangement of the signal terminals; and a test-purpose power source terminal connected to the power source terminal, and arrangement intervals of the test-purpose signal terminals and the test-purpose power source terminal are larger than an arrangement interval of the signal terminals.

Abstract: An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell.

Abstract: A demultiplexing apparatus includes a data obtainment unit to obtain the MP4 file data, and a decoding unit to demultiplex the MP4 file data obtained by the data obtainment unit into pairs of a moov and a mdat and pairs of a moof and a mdat, and decode those pairs pair-by-pair. A content duration specification unit specifies the content total duration based on the content total duration information contained in the moov of the MP4 file data obtained by the data obtainment unit and a playback unit displays the content total duration specified by the content duration specification unit.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.

Abstract: A BD-ROM on which a VC-1 video stream and an entry map (EP_map) are recorded. The VC-1 video stream includes: (a) picture data (I/P picture) whose first fields are the intra frame coding format and whose second fields are the inter frame predictive coding format; and (b) picture data (P/I picture) whose first fields are the inter frame predictive coding format and whose second fields are the intra frame coding format. The entry map indicates entry positions (SPN) of the I/P pictures, in correspondence with playback times (PTS), but does not indicate entry positions of the P/I pictures.

Abstract: An encoder is provided as one capable of accurately detecting an absolute value of an operating angle or the like of a scale plate in a simple configuration. In this encoder, each of light relay portions 4 formed along an operational direction ? in the scale plate has a pattern of a one-dimensional array of some of optically transparent potions 5 and optically nontransparent portions 6 different from those of the other light relay portions. This allows the encoder to identify the light relay portion 4 located on a light receiving region 100, based on second light intensity profile data VY(m), using the patterns as codes. In the identification of the light relay portion 4, the light relay portion 4 can be accurately identified with respect to a position of a reference light propagation portion 7 formed for each light relay portion 4 in the scale plate.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: In a data transmission system, a server is provided with a data storage unit which holds plural video streams having different I-frame intervals, as coded data corresponding to the same video sequence, and a data transmission unit for transmitting a predetermined video stream among the plural video streams, according to a command signal Sc from a receiving terminal. The receiving terminal transmits a data designation signal (command signal) Sc which designates one of the plural video streams stored at the server end, to the server, on the basis of the contents of user setting. Therefore, at the receiving terminal, a video stream to be supplied from the transmitting end (server) can be selected between one having a high resistance to transmission error and one having a high video quality, according to the user's preference.

Abstract: A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.