Abstract: The semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit; a data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to main memory unit. By means of the present invention, it is possible to efficiently conduct data transfer between a main memory unit and an auxiliary memory unit having different operational voltages, and moreover, it is possible to effectively suppress interior noise which is generated.

Abstract: Disclosed is an apparatus for demultiplexing multiplexed data. This apparatus comprises a demultiplexer for receiving a multiplexed packet stream in which a plurality of object data are multiplexed, and demultiplexing the multiplexed data with reference to packet identification numbers added to the respective packets; a decoder for decoding M pieces of object data separated from the multiplexed data, and outputting M pieces of decoded object data; a memory for storing N pieces of information relating to a program and separated by the demultiplexer; a memory for storing object composition information separated by the demultiplexer; a memory for storing information relating to the object data and separated by the demultiplexer; a compositor for compositing the M pieces of decoded object data; and an information analyzer for analyzing the packet identification numbers from the N pieces of information relating to the program, the object composition information, or the information relating to the object data.

Abstract: In a memory device which is used with the memory device connected to a data bus, the memory device includes an active termination circuit for terminating the memory device when the active termination circuit is electrically put into an active state and for unterminating the memory device when the active termination circuit is electrically put into an inactive state. The memory device further includes a control circuit for controlling the active termination circuit to electrically put the active termination circuit into the active state or the inactive state.

Abstract: A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.

Abstract: In a memory system having a memory controller 20 and at least one DRAM 30, the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM 30, and generates an internal reception clock signal for a DQ signal on the basis of the continuous and alternate inversion signal and a base clock signal. Then, the memory controller 20 counts the number of the receiving internal clocks from the moment an OUT1 command is issued to the DRAM 30 until a high-level data signal is received as the DQ data signal from the DRAM 30, and retains the count result as the number of delay clocks. Thus, the memory controller 20 can receive read data (DQ signal) on the basis of the internal reception clock signal when time equivalent to the number of the delay clocks passes after the read command is issued.

Abstract: A semiconductor device includes an input and output section, an internal circuit section, and a capacitance section. A signal is inputted to or outputted from the input and output section. The internal circuit section receives the signal inputted to the input and output section or outputs the signal via the input and output section. The capacitance section includes a capacitance connected to the input and output section. The signal is outputted on a signal transmitting line from the internal circuit section to the input and output section. The capacitance section is provided on a conductive line different from the signal transmitting line.

Abstract: A data transmission apparatus for relaying data transmitted from the transmitting end in units of packets, each packet having additional information relating to its sequence number, priority, and data reproduction time, comprises: a receiving unit for receiving packets transmitted from the transmitting end; a priority decision unit for deciding the priority of each of the received packets; a retransmission packet storage unit for storing packets the priorities of which are equal to or higher than a predetermined value, as retransmission packets, on the basis of the priority of each packet decided by the priority decision unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit for deciding whether retransmission of the packet for which the retransmission request has been made should be performed or not, on the basis of the retransmission request and the storage status of the retransmission packets in the retra

Abstract: When a server as a transmission source of content data is changed in a state where the content data from the server are played back in a receiving terminal, the receiving terminal receives the content data starting from the head of its not-yet-played portion to be played. A receiving terminal 100a for receiving content data transmitted from a server to be played is provided with a time information storage processing unit 105a for generating not-yet-played range information Ir indicating a range of a not-yet-played portion in the content data on the basis of time information concerning the playback process, which information is added to the content data in predetermined data units. When receiving a message for requesting to change the server S as the data transmission source, the receiving terminal 100a transmits a message requesting the content data to a new transmission source server with adding the not-yet-played range information to the data.

Abstract: A data reproduction apparatus comprises a data request unit for requesting a server to transmit data; a reception buffer for holding received data; a control unit for detecting the beginning position of AV data, and instructing a decoding unit to start decoding of the AV data when the amount of data stored in the reception buffer has reached a set value after detection of the beginning position position; a decoding unit for decoding the AV data stored in the reception buffer; a clock circuit for outputting a clock signal; and a display unit for displaying the decoded data. Since the AV data of the size required for data reproduction can be reliably pre-buffered when receiving the data, stable data reproduction can be carried out.

Abstract: The packet loss in a wired section is reported to a receiving terminal (61) using a loss notification packet from a gateway (62) located at the boundary between a wired section and a wireless section, and thus the causes for packet loss are separated. Also, using this loss notification packet, the packet loss rate in the wired section and the wireless section are separately calculated and the transmission rate and robustness of the data packets are determined with a sending terminal (60) in accordance with the respective loss rate of the sections.

Abstract: According to one embodiment, a virtual channel synchronous dynamic random access memory (VCSDRAM) (100) can perform a high-frequency test with lower frequency test equipment. The VCSDRAM (100) can include a command decoder circuit (102) that can receive a transfer command and provide a transfer command signal (124). A transfer operation start signal generating circuit (106) can receive and latch the transfer command signal (124). The command decoder circuit (102) can then receive an active command and provide an active command signal (120). The active command signal (120) can result in the generation of a main storage activating signal (128). Having latched the transfer command signal (124), the transfer operation start signal generating circuit (106) can generate a transfer operation start signal (130) in response to the active command signal (120). The transfer operation start signal (130) can generate a control signal (132).

Abstract: The semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory, and has a structure which permits bidirectional data transfer via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit; a data transfer bus line precharge power source circuit is provided which supplies to data transfer bus line, when data is not being transferred, a voltage having a level which is lower than the power source voltage supplied to main memory unit. By means of the present invention, it is possible to efficiently conduct data transfer between a main memory unit and an auxiliary memory unit having different operational voltages, and moreover, it is possible to effectively suppress interior noise which is generated.

Abstract: In a data transmission system, a server is provided with a data storage unit which holds plural video streams having different I-frame intervals, as coded data corresponding to the same video sequence, and a data transmission unit for transmitting a predetermined video stream among the plural video streams, according to a command signal Sc from a receiving terminal. The receiving terminal transmits a data designation signal (command signal) Sc which designates one of the plural video streams stored at the server end, to the server, on the basis of the contents of user setting. Therefore, at the receiving terminal, a video stream to be supplied from the transmitting end (server) can be selected between one having a high resistance to transmission error and one having a high video quality, according to the user's preference.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of the main memory portion and at least one of address input terminals assigning rows or columns of the sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of the main memory portion. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: The invention relates to a packet generating method for multiplexing one program composed of digital image, digital sound or digital data, or multiplexing and transmitting plural programs, a data multiplexing method using the same, and an apparatus for coding and decoding such transmission data, and the invention further relates to a packet generating method for generating a packet row of digital data, containing a change identifier for identifying change of digital data in the packet row, and multiplexing so that the packet containing this change identifier may be disposed closest to the packet containing the changed digital data, among packets containing various change identifiers in the packet row, a data multiplexing method using the same, and an apparatus for coding and decoding such transmission data.

Abstract: A decoding buffer capacity necessary for decoding N pieces of digital data, including a picture, audio, a character and another form of data, is found beforehand. Then the found capacity is compared with a predetermined value. M pieces of digital data are selected out of the N pieces of digital data so that a total buffer capacity necessary for decoding the M pieces of digital data is not more than the predetermined value. Then the M pieces of digital data are multiplexed and supplied as one multiplexed data. This data multiplexing method enables systems having different buffer capacities in their own decoders to exactly decode digital data by changing decoding buffer capacities that are predetermined. As a result, a transmission free from missing an important data is realized.

Abstract: A data transmission apparatus has a multiplexing unit that cyclically multiplexes presentation information and navigation information stored in a transmission data storage unit according to control by a multiplexing control unit and a transmission unit that transmits the multiplexed stream. The reception control unit of a data reception apparatus sets filter conditions in a filter condition storage unit of a TS decoder unit in accordance with user operation indications. The presentation information and navigation information separated by the TS decoder unit are outputted via a reproduction unit to a display unit and an audio output unit.

Abstract: In a data receiving terminal, a time stamp of the data whose reproduction has been terminated is stored in a memory when receiving/reproducing certain content, and when this certain content is reconnected to, a sending device (server) is requested to send data from the time stamp stored in the memory.

Abstract: A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.