Patents by Inventor Yoshinori Muramatsu

Yoshinori Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020076089
    Abstract: A fingerprint authentication apparatus has a combined visible/infrared light source, which illuminates a finger placed on an optical image sensor with both infrared light and visible light. The optical image sensor has a block with infrared sensitivity and a block within infrared sensitivity, and generates a fingerprint image from light scattered by the finger. The infrared sensitivity of the infrared-sensitive block of the optical image sensor is such that a clear image is obtained from a living organism, and an unclear image is obtained from a replica. If the finger is an actual living finger, the fingerprint images from both blocks are clear, but in the case of a replica, the image from the block having infrared sensitivity is clear, and the image from the block without having infrared sensitivity is unclear.
    Type: Application
    Filed: July 24, 2001
    Publication date: June 20, 2002
    Inventors: Yoshinori Muramatsu, Naoki Kitagawa
  • Publication number: 20020075390
    Abstract: An image sensor is disclosed that prevents a photoelectrically-converted signal from being corrupted during a readout operation. The image sensor includes a line-selection line located on an upper side of a pixel relative to a top to bottom scan direction and disposed across the pixel in a direction substantially perpendicular to the top to bottom scanning direction. A signal reset line is located on a lower side of the pixel relative to a top to bottom scan direction and is disposed across the pixel in a direction substantially perpendicular to the top to bottom scanning direction. The line-selection line and the signal-reset line are disposed above and below a photoelectric conversion portion of the pixel.
    Type: Application
    Filed: December 12, 2001
    Publication date: June 20, 2002
    Applicant: NEC CORPORATION
    Inventors: Yoshinori Muramatsu, Hiroaki Ohkubo
  • Publication number: 20020040961
    Abstract: The present invention provides a solid-state image pick-up device which is capable of displaying its image pick-up ability more than that of the related art. A sensor array is composed of photoelectric conversion cells arranged in the form of a matrix. An X scanner and a Y scanner scan the respective photoelectric conversion cells. A VGA amplifies output voltages of the respective photoelectric conversion cells, and an ADC converts an output voltage of the VGA into digital data. An average computing unit computes the average value of output voltages of the respective photoelectric conversion cells in a predetermined area of the sensor array on the basis of the output of the ADC. A divider divides a reference value by the average value and outputs the result of division to a multiplier.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 11, 2002
    Applicant: NEC CORPORATION
    Inventors: Fuyuki Okamoto, Teruyuki Higuchi, Yoshinori Muramatsu
  • Publication number: 20020015191
    Abstract: An image sensor includes (a) a pixel array, (b) a horizontal shift register horizontally scanning the pixel array, (c) a vertical shift register vertically scanning the pixel array to cooperate with the horizontal shift register for selecting a pixel among the pixel array, and (d) a horizontal blanking counter counting a horizontal blanking period and comprised of a shift register.
    Type: Application
    Filed: December 5, 2000
    Publication date: February 7, 2002
    Applicant: NEC Corporation
    Inventor: Yoshinori Muramatsu
  • Patent number: 6337580
    Abstract: A semiconductor integrated circuit which enables a subthreshold current to be suppressed when a logic gate circuit group is nonactivated and enables the logic gate circuit group to be activated at a high speed is provided. The semiconductor integrated circuit has at least one logic gate circuit connected to a feed line, a first transistor serially connected to the feed line in order to suppress the subthreshold current flowing in the logic gate circuit upon nonactivation of the logic gate circuit and a second transistor which is connected in parallel to the first transistor. The second transistor is activated prior to activation of the logic gate circuit and the first transistor.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: January 8, 2002
    Assignee: NEC Corporation
    Inventor: Yoshinori Muramatsu
  • Publication number: 20020000508
    Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.
    Type: Application
    Filed: June 12, 2001
    Publication date: January 3, 2002
    Applicant: NEC Corporation
    Inventors: Yoshinori Muramatsu, Susumu Kurosawa, Hiroaki Ohkubo, Tsuyoshi Nagata, Yasutaka Nakashiba
  • Publication number: 20010052574
    Abstract: There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned ‘ON/OFF’ in any one of the pixels and any one of the readout portions are all kept in ‘ON’ state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 20, 2001
    Inventors: Susumu Kurosawa, Yoshinori Muramatsu
  • Publication number: 20010026169
    Abstract: A semiconductor integrated circuit which enables a subthreshold current to be suppressed when a logic gate circuit group is nonactivated and enables the logic gate circuit group to be activated at a high speed is provided. The semiconductor integrated circuit has at least one logic gate circuit connected to a feed line, a first transistor serially connected to the feed line in order to suppress the subthreshold current flowing in the logic gate circuit upon nonactivation of the logic gate circuit and a second transistor which is connected in parallel to the first transistor. The second transistor is activated prior to activation of the logic gate circuit and the first transistor.
    Type: Application
    Filed: April 8, 1999
    Publication date: October 4, 2001
    Inventor: YOSHINORI MURAMATSU
  • Publication number: 20010005226
    Abstract: An image sensor and a pixel reading method used this image sensor, in which the accuracy of a black level can be increased by that an optical black region being the black level reference of signals is read every horizontal line at a local or random access mode, are provided. And also the structure of a camera system used this image sensor can be simplified is provided. The image sensor is a MOS type image sensor composed of a pixel array region and an optical black region disposed at the one end in the pixel array region. And the MOS type image sensor provides a mode selector that selects the local access or random access mode or a frame access mode. When the local access or random access mode is activated, the image sensor decides a pixel reading region in the pixel array region. The image sensor reads information of one or more pixels having a designated horizontal line address in the pixel reading region every horizontal line address.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 28, 2001
    Applicant: NEC CORPORATION
    Inventors: Yoshinori Muramatsu, Hidemitsu Nikou
  • Patent number: 6191409
    Abstract: An image sensor comprises conversion cells (41ij) arranged into a matrix for generating conversion voltage in response to incident light, and a processing section for performing a processing of deriving the conversion voltage. The conversion cells comprise a transistor and a photodiode for changing, after predetermined voltage is set with the initial setting of the processing section, the predetermined voltage in response to incident light and outputting it as the conversion voltage, a transistor for amplifying the conversion voltage, a transistor for outputting the amplified conversion voltage to the processing section, and a transistor for applying voltage corresponding to the threshold of the transistor to predetermined voltage set to the photodiode upon the initial setting.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: February 20, 2001
    Assignee: NEC Corporation
    Inventor: Yoshinori Muramatsu