Patents by Inventor Yoshinori Muramatsu

Yoshinori Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050237408
    Abstract: A CMOS color image sensor, which is a solid-state image pickup device, includes a plurality of pixels arranged in a matrix having a plurality of rows and a plurality of columns, each of the plurality of pixels converting the incident light intensity into an electrical signal; a pixel array including the plurality of pixels; row-selection lines; and column-reading lines. Two column-reading lines are provided for each column of the pixel array. Pixels in even rows of each column are connected to one column-reading line and pixels in odd rows of each column are connected to the other column-reading line.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 27, 2005
    Inventor: Yoshinori Muramatsu
  • Publication number: 20050231624
    Abstract: In a solid-state imaging device including an analog-to-digital converter, a clock converter that generates a high-speed clock that is faster than a master clock is provided. A voltage comparator compares a pixel signal input from a vertical signal line for each row control line with a reference voltage, generating pulses having magnitudes corresponding to a reset component or a signal component in a temporal direction. A counter counts the width of pulse signals until completion of the comparison in the voltage comparator based on a clock that is generated based on the high-speed clock, holding a count value at a time of completion of the comparison. A communication and timing controller exercises control so that the voltage comparator performs comparison for the reset component and the counter performs down-counting in a first processing iteration and so that the voltage comparator performs comparison for the signal component and the counter performs up-counting in a second processing iteration.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 20, 2005
    Inventors: Yoshinori Muramatsu, Noriyuki Fukushima, Yoshikazu Nitta, Yukihiro Yasui
  • Patent number: 6954111
    Abstract: At the same control voltage Vtune, the oscillation frequency with only switches SW3 and SW4 being closed is higher than that with only switches SW1 and SW2 being closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SW1 and SW2 being closed and the capacitance of varactor diodes D1 and D2 cannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SW3 and SW4 to control the capacitance of the varactor diodes D1 and D2. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SW1 to SW4, while a fine tuning can be performed with the varactor diodes D1 and D2. Consequently, the range of the oscillation frequency is increased.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: October 11, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Fuyuki Okamoto
  • Publication number: 20050206548
    Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.
    Type: Application
    Filed: February 16, 2005
    Publication date: September 22, 2005
    Inventors: Yoshinori Muramatsu, Noriyuki Fukushima, Yoshikazu Nitta, Yukihiro Yasui
  • Publication number: 20050195304
    Abstract: A CMOS image sensor includes column-parallel ADCs. Each of the ADCs includes a comparator and an up/down counter. With this configuration, digital values of pixels in a plurality of rows can be added without using additional circuits, such as an adder and a line memory device, and the frame rate can be increased while maintaining constant sensitivity.
    Type: Application
    Filed: February 16, 2005
    Publication date: September 8, 2005
    Inventors: Yoshikazu Nitta, Noriyuki Fukushima, Yoshinori Muramatsu, Yukihiko Yasui
  • Patent number: 6900837
    Abstract: An image sensor and a pixel reading method used this image sensor, in which the accuracy of a black level can be increased by that an optical black region being the black level reference of signals is read every horizontal line at a local or random access mode, are provided. And also the structure of a camera system used this image sensor can be simplified is provided. The image sensor is a MOS type image sensor composed of a pixel array region and an optical black region disposed at the one end in the pixel array region. And the MOS type image sensor provides a mode selector that selects the local access or random access mode or a frame access mode. When the local access or random access mode is activated, the image sensor decides a pixel reading region in the pixel array region. The image sensor reads information of one or more pixels having a designated horizontal line address in the pixel reading region every horizontal line address.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: May 31, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Hidemitsu Nikou
  • Patent number: 6888956
    Abstract: A fingerprint authentication apparatus has a combined visible/infrared light source, which illuminates a finger placed on an optical image sensor with both infrared light and visible light. The optical image sensor has a block with infrared sensitivity and a block within infrared sensitivity, and generates a fingerprint image from light scattered by the finger. The infrared sensitivity of the infrared-sensitive block of the optical image sensor is such that a clear image is obtained from a living organism, and an unclear image is obtained from a replica. If the finger is an actual living finger, the fingerprint images from both blocks are clear, but in the case of a replica, the image from the block having infrared sensitivity is clear, and the image from the block without having infrared sensitivity is unclear.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: May 3, 2005
    Assignee: NEC Electroncs Corporation
    Inventors: Yoshinori Muramatsu, Naoki Kitagawa
  • Publication number: 20040251978
    Abstract: There is provided an LC-VCO in which two spiral inductors are provided in the topmost layers of multilayer interconnection layer, while varactor elements and N-channel transistors are positioned in an underlying region of the two spiral inductors on a surface of a semiconductor substrate, the region excluding the center axes of the spiral inductors. This allows for providing a reduced layout area for the LC-VCO and preventing magnetic fields created by the spiral inductors from having adverse effects on the operation of the varactor elements and the N-channel transistors.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 16, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Yasutaka Nakashiba
  • Publication number: 20040228561
    Abstract: A structure supporting a differential rotatably includes an inner ring arranged at the differential, an outer ring arranged at an external peripheral portion formed to surround the differential, and a tapered roller rolling between the inner ring and the outer ring. At least any one of the inner ring, the outer ring and the tapered roller has a carbo-nitrided layer and provides an austenite grain number falling within a range exceeding 10. Thus the structure can be provided with increased anti-crack strength and dimensional stability, and increased rolling contact fatigue life.
    Type: Application
    Filed: February 27, 2004
    Publication date: November 18, 2004
    Inventors: Kouichi Okugami, Yoshinori Muramatsu, Chikara Ohki
  • Publication number: 20040170348
    Abstract: A transmission component is incorporated into a transmission in which an input shaft, an output shaft, or a gear is rotatably supported by a rolling bearing. The component has a nitriding layer at a surface layer and an austenite grain with a grain size number falling within a range exceeding 10. This provides a transmission component having an increased anti-crack strength, enhanced dimensional stability, and a long fatigue life. A method of manufacturing such a transmission component and a tapered roller bearing are also provided.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 2, 2004
    Applicant: NTN CORPORATION
    Inventors: Kouichi Okugami, Yoshinori Muramatsu, Chikara Ohki, Michio Hori
  • Publication number: 20040169564
    Abstract: In a high-stability low-noise voltage-controlled oscillator, a current mirror circuit is connected with a power supply line, and a current controller for controlling a current flowing through the current mirror circuit is disposed between the current mirror circuit and a ground line. In parallel with the current controller, a first negative resistor, an LC circuit, and a second negative resistor are disposed in this order between the current mirror circuit and the ground line. The LC circuit includes an inductor, two variable capacitance elements, and three capacitor pairs. Three control signals are applied such that each control signal is applied to one of N-channel transistors in the current controller and also to one of switch pairs corresponding to one of capacitor pairs in a resonator.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 2, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoshinori Muramatsu
  • Publication number: 20040150485
    Abstract: The LC-VCO is provided with two negative resistance units and an LC circuit unit. The LC circuit unit has two output terminals. An inductor is connected between the output terminals, and a series of variable capacitors is connected in parallel with the inductor. In the LC circuit unit, a variable capacitor is connected between one of the output terminals and a node. Another variable capacitor is connected between the other output terminal and another node. Switches are connected between the nodes and a ground potential line, respectively, and between the nodes and a power supply potential line, respectively.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Yoshinori Muramatsu
  • Publication number: 20040080374
    Abstract: An LC circuit section and a negative resistance section are provided for an LC-VCO. A pair of output terminals are provided for the LC circuit section and an inductor is connected between the output terminals, and two variable capacitors are connected in series to each other parallelly with the inductor. Further, the LC circuit section is provided with a pair of capacitors and a pair of switches that are connected between the capacitors and a ground potential and consist of NMOS transistors. Moreover, a switch that consists of the NMOS transistor is connected between a node, which is between one capacitor and one switch, and a node, which is between the other capacitor and the other switch, and the two nodes are connected to each other when the switch is closed.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 29, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Yoshinori Muramatsu
  • Patent number: 6690000
    Abstract: According to an image sensor disclosed, a pixel circuit includes a photo-diode 14 for generating a photo-electric conversion voltage which corresponds to an input optical level, a transistor 11 which is activated in response to a Reset signal RST, to initialize the photo-diode 14 from a power supply VDD, a transistor 12 which, when connected between the power supply VDD and a bit line BL, amplifies a photo-electric conversion voltage and outputs it onto the bit line BL, and a transistor 13 which is activated by a word-line readout control signal WL, to interconnect the transistor 12 and the bit line BL, in which the transistor 11 is of a depletion type.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: February 10, 2004
    Assignee: NEC Corporation
    Inventors: Yoshinori Muramatsu, Susumu Kurosawa, Yasutaka Nakashiba, Tsuyoshi Nagata
  • Patent number: 6667468
    Abstract: There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned ‘ON/OFF’ in any one of the pixels and any one of the readout portions are all kept in ‘ON’ state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: December 23, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Susumu Kurosawa, Yoshinori Muramatsu
  • Patent number: 6667767
    Abstract: There is disclosed an image sensor wherein the dispersion in threshold voltages of a transistor constituting a source follower for outputting a signal is compensated. The disclosed image sensor is provided with a coupling capacitor to which an output voltage of a pixel is applied through a transistor and with a transistor of a source follower to read out a voltage at the node S/Hn of the coupling capacitor.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: December 23, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Susumu Kurosawa
  • Publication number: 20030146799
    Abstract: At the same control voltage Vtune, the oscillation frequency with only switches SW3 and SW4 being closed is higher than that with only switches SW1 and SW2 being closed. Accordingly, even when the oscillation frequency is lower than designed with only the switches SW1 and SW2 being closed and the capacitance of varactor diodes D1 and D2 cannot be controlled to provide the desired oscillation frequency, the desired oscillation frequency can be provided by closing only the switches SW3 and SW4 to control the capacitance of the varactor diodes D1 and D2. On the oscillation frequency, a coarse tuning can be performed by controlling the switches SW1 to SW4, while a fine tuning can be performed with the varactor diodes D1 and D2. Consequently, the range of the oscillation frequency is increased.
    Type: Application
    Filed: January 28, 2003
    Publication date: August 7, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshinori Muramatsu, Fuyuki Okamoto
  • Patent number: 6576882
    Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: June 10, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Yoshinori Muramatsu, Susumu Kurosawa, Hiroaki Ohkubo, Tsuyoshi Nagata, Yasutaka Nakashiba
  • Publication number: 20020153474
    Abstract: The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.
    Type: Application
    Filed: June 19, 2002
    Publication date: October 24, 2002
    Applicant: NEC Corporation
    Inventors: Yoshinori Muramatsu, Susumu Kurosawa, Hiroaki Ohkubo, Tsuyoshi Nagata, Yasutaka Nakashiba
  • Patent number: 6455909
    Abstract: A MOS type image sensor including a plurality of pixel array sections each including, as interconnects traversing the pixel array section, a signal reset line and a row selection line stacked with each other and sandwiching a dielectric film. In the image sensor, the areas of the signal reset line and the row selection line occupied in the pixel section can be reduced to consequently increase the area of the light-receiving section occupied in the pixel section, thereby increasing the sensitivity to light.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: September 24, 2002
    Assignee: NEC Corporation
    Inventors: Yoshinori Muramatsu, Tsuyoshi Nagata