Abstract: There are increasing needs of searching on which data in a storage circuit is most similar to input information from the outside. Expectations for storage circuits having such memory techniques are high, and to enable a computer to handle information from the outside more flexibly is considered an essential technique. To achieve such techniques, a storage circuit needs to have a function of measuring a degree of similarity between stored data and input data. In an approximate-search-circuit, a memory matrix of a conventional storage circuit is caused to function as a data conversion circuit for calculating the inner-product distance between stored data and input data, by inputting the input data to the memory matrix in the form of a time series of pulse-signals, and the location of stored data with the highest inner-product is output from a circuit that calculates the inner-product in real time.

Abstract: There are increasing needs of searching on which data in a storage circuit is most similar to input information from the outside. Expectations for storage circuits having such memory techniques are high, and to enable a computer to handle information from the outside more flexibly is considered an essential technique. To achieve such techniques, a storage circuit needs to have a function of measuring a degree of similarity between stored data and input data. In an approximate-search-circuit, a memory matrix of a conventional storage circuit is caused to function as a data conversion circuit for calculating the inner-product distance between stored data and input data, by inputting the input data to the memory matrix in the form of a time series of pulse-signals, and the location of stored data with the highest inner-product is output from a circuit that calculates the inner-product in real time.

Abstract: Disclosed herein is a semiconductor integrated circuit which controls the quality of an image and includes a viewer detector, a region specifier, and a controller. The viewer detector detects the number of viewer(s) watching the image and a gaze region being watched by the viewer within the image. If the number of viewers is plural, the region specifier specifies a local region of the image as a target region based on a plurality of gaze regions being watched by the viewers. The controller performs image quality control on the target region.

Abstract: A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

Abstract: Disclosed herein is a semiconductor integrated circuit which controls the quality of an image and includes a viewer detector, a region specifier, and a controller. The viewer detector detects the number of viewer(s) watching the image and a gaze region being watched by the viewer within the image. If the number of viewers is plural, the region specifier specifies a local region of the image as a target region based on a plurality of gaze regions being watched by the viewers. The controller performs image quality control on the target region.

Abstract: A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.

Abstract: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.

Abstract: An audio synchronizer for a digital television broadcast has a clock generation section that generates a fundamental clock pulse by demultiplying a clock pulse of a given frequency, which is generated by multiplying an input clock pulse, by a predetermined demultiplication ratio; a comparison section that compares reference time information included in a broadcast wave with time information counted by means of the fundamental clock pulse generated by the clock generation section; a control section that commands the clock generation section to adjust a frequency of the fundamental clock pulse in accordance with information about a time difference acquired from the comparison section; a sampling clock generation section that generates a sampling clock pulse on the basis of the fundamental clock pulse; and a sampling rate conversion section that performs sampling conversion so as to synchronize the audio sampling clock pulse and audio data included in the broadcast wave with a sampling clock pulse of an audio DA

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input terminals and a plurality of output terminals. Signals are transmitted through the loop in a single specified direction in synchronization with a clock signal. Each of the macro circuits receives the signals at the input terminals thereof, accepts the signals if the signals are destined for the macro circuit, and transfers the signals to the output terminals thereof if the signals are not destined for the macro circuit. Even if the macro circuits simultaneously transmit signals, the electronic circuit system transmits the signals in the specified direction through the loop in synchronization with the clock signal up to destination macro circuits.

Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

Abstract: Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.