Abstract: A semiconductor memory device which includes a high potential source, a low potential source, and a word line driver portion which makes the potential of selected word lines a selection level lower by a predetermined potential than the high potential source. Memory cells are connected to the word lines. A first low potential source or a second potential source is connected to the low potential source. A plurality of transistors are provided in the word line driver portion so as to connect a plurality of stages. When the memory has a sufficient power source margin, the word line driver is formed as a two-stage device so as enable high speed operation. When the memory has an unsufficient power source margin, the word line driver is formed as a one-stage device so as to ensure a sufficient power source margin.

Abstract: A two-stage decoder circuit includes a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level, and the second-stage decoder circuit is formed by a diode-matrix circuit.

Abstract: In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a wiring layer for a word line or a bit line, so that the switching speed can be increased and the memory cell area can be decreased.

Abstract: In a semiconductor device including a plurality of input signal pads (P.sub.0, . . . , P.sub.7); a plurality of emitter followers (Q.sub.01, . . . , Q.sub.71) are connected to the input signal pads (P.sub.0, . . . , P.sub.7); a plurality of input signal buffers (BUF.sub.0, . . . , BUF.sub.7) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71); and a plurality of constant current sources (I.sub.01, . . . , I.sub.71) are connected to the emitter followers (Q.sub.01, . . . , Q.sub.71). The emitter followers (Q.sub.01, . . . , Q.sub.71) are in proximity to the input signal pads (P.sub.0, . . . , P.sub.7), and the constant current sources (I.sub.0, . . . , I.sub.7) are in proximity to the emitter followers (Q.sub.01, . . . , Q.sub.71) . The current values of the constant current sources (I.sub.01, . . . , I.sub.71 ) are determined in accordance with the length of the corresponding connections between the emitter followers (Q.sub.01, . . . , Q.sub.71) and the input signal buffers (BUF.sub.0, . . .

Abstract: A semiconductor device including a plurality of resistors. All the resistors are contained in circuit block regions which are arranged successively in a first direction. Each of the resistors is extended in the first direction. All of the resistors are set up in the form of a plurality of stages arranged in a second direction perpendicular to the first direction and in parallel with each other.

Abstract: A semiconductor memory comprising at least memory cells, word lines (W.sub.+, W.sub.-), bit lines (BL, BL) and word line discharge circuits to be co-operated together with a word line discharge current controller. The word line discharge current controller is operative to gradually reduce a word line discharge current absorbed from the word line W.sub.- to the word line discharge circuit together with a gradual attenuation of an inverse current from the bit line to the corresponding memory cell.

Abstract: A semiconductor memory device includes a plurality of static-type memory cells connected to pairs of word lines, each word line pair being composed of a word line having a high potential and a word line having a low potential, and a plurality of word-line discharging circuits, each being connected to one of the word line pairs. Each of the word-line discharging circuits includes, a thyristor whose anode is connected, via a voltage level shifter, to a word line having a high potential and whose cathode is connected to a constant-current source or a constant-voltage source. The thyristor comprises a PNP transistor and an NPN transistor. The NPN transistor can be a multi-emitter transistor or a multi-collector transistor whose second emitter or collector is connected to a word line having a low potential.