Abstract: A memory cell array ARY includes a plurality of sub-arrays SARY. A data transfer unit DTU alternately accesses the sub-arrays SARY to transfer data between the sub-arrays SARY. Accordingly, it is possible to transfer data stored in one of the sub-arrays SARY to another sub-array SARY without outputting the data to a bus connected to a semiconductor memory MEM. For example, a microcontroller CNT in a system MSYS can use the bus during the data transfer since the bus is not used for the data transfer. As a result, it is possible to prevent the performance of the system MSYS from being deteriorated due to the data transfer.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.

Abstract: A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.

Abstract: A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.

Abstract: Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

Abstract: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A memory device includes a plurality of blocks, each being capable of carrying out different types of operations, and a control unit for selecting one block after another from the plurality of blocks. In this memory device, each selected block upon a selection thereof starts carrying out the operations in a predetermined order in a pipeline operation. The memory device may include an array of memory cells, a word line selecting circuit, a row address register circuit, sense amplifiers, a precharge circuit, a global row scheduler for successively selecting two or more blocks to simultaneously perform respective operations, and a check unit. The check unit detects consecutive accesses that are made by the global row scheduler to a single block, thereby causing the global row scheduler to delay or ignore the block selection of the single block.