Patents by Inventor Yoshinori Sakamoto

Yoshinori Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050267277
    Abstract: The composition for forming an anti-reflective coating film of the present invention has a hard-volatility and high coating performance. In particular, when the 193 nm ArF excimer laser beam source is applied, the composition exhibits a higher etching property. Therefore, the composition is suitably for forming an anti-reflective coating film with no voids and for a method of forming resist patterns using the composition. The composition for forming an anti-reflective coating film comprising; (A) a hard-volatility light absorbing compound, (B) siloxanepolymer, and (C) a solvent.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 1, 2005
    Inventors: Masaru Takahama, Yoshinori Sakamoto, Takeshi Tanaka, Naoki Yamashita
  • Publication number: 20050092206
    Abstract: To provide a silica film-forming material having a low dielectric constant and giving a film of less undergoing change in aging, a coating solution for forming a silica film includes a hydrolysis product of a mixture comprising: a tetraalkoxysilane; and at least one of a monoalkyltrialkoxysilane and a dialkyldialkoxysilane, and an ammonium salt represented by formula (I): wherein R1 represents an alkyl group having from 6 to 30 carbon atoms, R2 represents an alkyl group having from 1 to 5 carbon atoms, and X represents CH3COO, SO3H or OH.
    Type: Application
    Filed: October 13, 2004
    Publication date: May 5, 2005
    Inventors: Yoshinori Sakamoto, Naoki Yamashita
  • Publication number: 20050048160
    Abstract: The present invention provides an improved multi-mold apparatus for manufacturing friction members, with each mold composed of a set comprising a first (top) mold, a second (bottom) mold, and a frame mold. The apparatus is capable of correcting any misalignment in the mountings of the plurality of molds and accurately aligning the molds by movably supporting at least one of the first mold, the second mold and the third mold by first, second and frame bases, respectively, so that the base and molds are movable laterally, in a direction perpendicular to the direction of advance. Projections are formed on one of the first mold and either the frame mold or the back plate and bonding through-holes are formed on the remaining mold or the back plate, so that the projections engage the holes so as to align the first mold and the frame mold accurately.
    Type: Application
    Filed: June 10, 2004
    Publication date: March 3, 2005
    Inventors: Yoshinori Sakamoto, Masanori Ueno
  • Patent number: 6797092
    Abstract: A method for manufacturing a monolithic ceramic electronic component formed by using a laminate allows a plurality of types of ceramic green sheets to be laminated with ease and efficiency. The method enables a reduction in space for lamination. This method includes first, a ceramic green sheet with a predetermined shape is cut out of a long first ceramic green sheet supported on a carrier film by a cutting/laminating head. The cut-out ceramic green sheet is laminated to the cutting/laminating head. A card-like second ceramic green sheet supported on a carrier film is cut by a cutting/laminating head. The cut ceramic green sheets is laminated to the cutting/laminating head. A laminate is formed by performing each of the first and second steps plural times.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: September 28, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinori Sakamoto, Kengo Shimizu
  • Patent number: 6786867
    Abstract: In order to allow operation of key switches without awkwardly bending the elbow or wrist, and arranging key switches aesthetically in the appearance design while preventing confusion in operation and eliminating dead space within the area occupied by the key switches, key switches 1-1-1-6 are arranged horizontally in a row slantingly with respect to the horizontal and vertical directions of an operation panel 101.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: September 7, 2004
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Shinichi Amemiya, Osamu Furuta, Yoshinori Sakamoto
  • Publication number: 20040095809
    Abstract: The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 20, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Yoshinori Sakamoto, Tatsuya Bando
  • Patent number: 6683810
    Abstract: A non-volatile memory has a plurality of word lines, a plurality of bit lines and a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at the intersections of the plurality of word lines and the plurality of bit lines, and electrically performing operations to write and erase the stored information. A write control circuit for controlling the electric charges accumulated at the floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on the memory elements, carries out one or more each of search write operations, set to a smaller write quantity than the prescribed write quantity at the time of start of writing, and verify operations matching thereto.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: January 27, 2004
    Assignee: Renesas Technology Corporation
    Inventor: Yoshinori Sakamoto
  • Patent number: 6665176
    Abstract: In order to provide an electronic device permitting a reduction in size or an expansion of its internal space while maintaining its mechanical strength, a structure having mechanical strength is integrally formed with hinges for fitting a lid-shaped display unit to a box-shaped body and a carrying handle projecting outward from the box-shaped body.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: December 16, 2003
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Shinichi Amemiya, Osamu Furuta, Yoshinori Sakamoto
  • Publication number: 20030053356
    Abstract: A non-volatile memory and a method of non-volatile memory programming reduced in the frequency of fault occurrence and improved in the convenience of use while realizing stable write operations and shortening the substantial length of time required for writing is provided.
    Type: Application
    Filed: October 15, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventor: Yoshinori Sakamoto
  • Patent number: 6515073
    Abstract: An anti-reflective coating-forming composition comprising: (A) at least one compound selected from the group consisting of (i) a compound represented by the following formula (1): Si(OR1)a(OR2)b(OR3)c(OR4)d  (1) (ii) a compound represented by the following formula (2): R5Si(OR6)e(OR7)f(OR8)g  (2) and (iii) a compound represented by the following formula (3): R9R10Si(OR11)h(OR12)I  (3) and (B) a thermosetting resin which can be condensed to said component (A) and has an absorption capacity with respect to exposing light.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yoshinori Sakamoto, Katsumi Omori, Yoshio Hagiwara
  • Publication number: 20030018254
    Abstract: In order to allow operation of key switches without awkwardly bending the elbow or wrist, and arranging key switches aesthetically in the appearance design while preventing confusion in operation and eliminating dead space within the area occupied by the key switches, key switches 1-1-1-6 are arranged horizontally in a row slantingly with respect to the horizontal and vertical directions of an operation panel 101.
    Type: Application
    Filed: April 23, 2002
    Publication date: January 23, 2003
    Inventors: Shinichi Amemiya, Osamu Furuta, Yoshinori Sakamoto
  • Publication number: 20020181193
    Abstract: In order to provide an electronic device permitting a reduction in size or an expansion of its internal space while maintaining its mechanical strength, a structure having mechanical strength is integrally formed with hinges for fitting a lid-shaped display unit to a box-shaped body and a carrying handle projecting outward from the box-shaped body.
    Type: Application
    Filed: June 3, 2002
    Publication date: December 5, 2002
    Inventors: Shinichi Amemiya, Osamu Furuta, Yoshinori Sakamoto
  • Patent number: 6490201
    Abstract: A non-volatile memory and a method of non-volatile memory programming reduced in the frequency of fault occurrence and improved in the convenience of use while realizing stable write operations and shortening the substantial length of time required for writing is provided.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: December 3, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Yoshinori Sakamoto
  • Publication number: 20020157225
    Abstract: A method for manufacturing a monolithic ceramic electronic component formed by using a laminate allows a plurality of types of ceramic green sheets to be laminated with ease and efficiency. The method enables a reduction in space for lamination. This method includes first, a ceramic green sheet with a predetermined shape is cut out of a long first ceramic green sheet supported on a carrier film by a cutting/laminating head. The cut-out ceramic green sheet is laminated to the cutting/laminating head. A card-like second ceramic green sheet supported on a carrier film is cut by a cutting/laminating head. The cut ceramic green sheets is laminated to the cutting/laminating head. A laminate is formed by performing each of the first and second steps plural times.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 31, 2002
    Inventors: Yoshinori Sakamoto, Kengo Shimizu
  • Patent number: 6409844
    Abstract: An article of magnesium or its alloy having a surface layer containing magnesium condensed phosphate and magnesium phosphate, which can be produced by treating an article of magnesium or its alloy with a treating liquid containing 1,000 to 20,000 ppm of alkaline metal ions, 1,000 to 50,000 ppm of condensed phosphate ions, and 100 to 20,000 ppm of borate ions, and having pH of at least 8. The treated article has good corrosion resistance, and a coating can be formed on the surface of the article with good adhesion.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: June 25, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naohiro Shikata, Yoshiaki Kondou, Yukio Nishikawa, Yoshihiko Nishizawa, Yoshinori Sakamoto, Takeshi Fujiwaki
  • Publication number: 20020057598
    Abstract: A non-volatile memory and a method of non-volatile memory programming reduced in the frequency of fault occurrence and improved in the convenience of use while realizing stable write operations and shortening the substantial length of time required for writing is provided.
    Type: Application
    Filed: March 19, 2001
    Publication date: May 16, 2002
    Inventor: Yoshinori Sakamoto
  • Patent number: 6374820
    Abstract: A manufacturing method for a monolithic ceramic part permitting a ceramic laminate to be cut stably and speedily, even if the thickness of the ceramic laminate is large. In order to divide a mother ceramic laminate into individual laminates of monolithic ceramic part units, the ceramic laminate is cut with a cutting blade, using a pair of guides disposed on opposite sides of the cutting blade in the vicinity of one principal plane of the ceramic laminate to control the cutting direction, and then individual ceramic laminates thus obtained by cutting are fired.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: April 23, 2002
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yoshinori Sakamoto, Shizuma Tazuke, Haruhiko Mori
  • Publication number: 20010036998
    Abstract: An anti-reflective coating-forming composition comprising: (A) at least one compound selected from the group consisting of (i) a compound represented by the following formula (1):
    Type: Application
    Filed: March 26, 2001
    Publication date: November 1, 2001
    Inventors: Yoshinori Sakamoto, Katsumi Omori, Yoshio Hagiwara
  • Patent number: 6243313
    Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: June 5, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima
  • Patent number: 6226212
    Abstract: In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data reading time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: May 1, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Sakamoto, Tatsuya Ishii, Atsushi Nozoe, Hitoshi Miwa, Kazuyoshi Oshima