Patents by Inventor Yoshinori Tsuchiya
Yoshinori Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240117087Abstract: A method for producing a fluoropolymer which method includes polymerizing a perfluoromonomer in an aqueous medium in the presence of a polymer (1) to obtain a fluoropolymer, wherein the content of a polymerized unit derived from the perfluoromonomer in the fluoropolymer is 90 mol % or more based on all polymerized units of the fluoropolymer, the polymer (1) is a polymer of a monomer (1) represented by the general formula (1): CF2?CF—O—R-(Rf-SO3M)m, a polymerized unit (1) derived from the monomer (1) in the polymer (1) is 50% by mass or more based on all polymerized units of the polymer (1), and the content of a dimer and a trimer of the monomer (1) in the polymer (1) is 1.0% by mass or less based on the polymer (1).Type: ApplicationFiled: November 17, 2023Publication date: April 11, 2024Applicant: DAIKIN INDUSTRIES, LTDInventors: Yoshinori NANBA, Rina TAMAI, Takuma IWASAKA, Soushi TSUCHIYA, Kenji ICHIKAWA, Taketo KATO, Masaki IRIE, Taku YAMANAKA
-
Patent number: 11877883Abstract: A biological sound detection device includes a housing, a medium, a transducer unit, a detection unit, and a pressure adjusting unit. The medium has an acoustic impedance closer to water than air. The transducer unit is arranged in the housing, and converts a biological sound transmitted through the medium into an electric signal. The detection unit provides, together with the housing, an accommodation region that accommodates the medium, detects the biological sound, transmits the biological sound to the medium, and is deformable in a direction approaching the transducer unit according to a load of a physical body. The pressure adjusting unit adjusts a pressure of the medium so as to suppress an increase in the pressure of the medium due to deformation of the detection unit.Type: GrantFiled: August 2, 2022Date of Patent: January 23, 2024Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies CorporationInventors: Fan Cheng, Yuki Anno, Yoshinori Tsuchiya
-
Publication number: 20230402049Abstract: A microphone system causes a microphone disposed in an acoustic space to collect sound, classifies a sound included in a sound data related to the sound collected by the microphone into a type of speech sound of a human present in the acoustic space and a type of noise that is a sound other than the speech sound based on a value related to a reflection sound reflected in the acoustic space, and outputs data related to the classified speech sound to a speech recognition device.Type: ApplicationFiled: May 19, 2023Publication date: December 14, 2023Inventors: Tomoki TANEMURA, Takashi TAKAZAWA, Yoshinori TSUCHIYA, Masaaki KAWAUCHI
-
Publication number: 20230042847Abstract: A biological sound detection device includes a housing, a medium, a transducer unit, a detection unit, and a pressure adjusting unit. The medium has an acoustic impedance closer to water than air. The transducer unit is arranged in the housing, and converts a biological sound transmitted through the medium into an electric signal. The detection unit provides, together with the housing, an accommodation region that accommodates the medium, detects the biological sound, transmits the biological sound to the medium, and is deformable in a direction approaching the transducer unit according to a load of a physical body. The pressure adjusting unit adjusts a pressure of the medium so as to suppress an increase in the pressure of the medium due to deformation of the detection unit.Type: ApplicationFiled: August 2, 2022Publication date: February 9, 2023Inventors: FAN CHENG, YUKI ANNO, YOSHINORI TSUCHIYA
-
Patent number: 10714606Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.Type: GrantFiled: September 5, 2016Date of Patent: July 14, 2020Assignee: DENSO CORPORATIONInventors: Youngshin Eum, Kazuhiro Oyama, Yasushi Higuchi, Yoshinori Tsuchiya, Shinichi Hoshi
-
Patent number: 10381469Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: GrantFiled: August 28, 2014Date of Patent: August 13, 2019Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Shinichi Hoshi, Kazuyoshi Tomita, Kenji Itoh, Masahito Kodama, Tsutomu Uesugi
-
Patent number: 10121663Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.Type: GrantFiled: March 26, 2015Date of Patent: November 6, 2018Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Hiroyuki Tarumi, Shinichi Hoshi, Masaki Matsui, Kenji Itoh, Tetsuo Narita, Tetsu Kachi
-
Patent number: 10084052Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.Type: GrantFiled: September 14, 2015Date of Patent: September 25, 2018Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Shinichi Hoshi, Masaki Matsui, Kenji Itoh
-
Publication number: 20180248026Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.Type: ApplicationFiled: September 5, 2016Publication date: August 30, 2018Inventors: Youngshin EUM, Kazuhiro OYAMA, Yasushi HIGUCHI, Yoshinori TSUCHIYA, Shinichi HOSHI
-
Publication number: 20170301765Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.Type: ApplicationFiled: September 14, 2015Publication date: October 19, 2017Inventors: Yoshinori TSUCHIYA, Shinichi HOSHI, Masaki MATSUI, Kenji ITOH
-
Publication number: 20170162391Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.Type: ApplicationFiled: March 26, 2015Publication date: June 8, 2017Inventors: Yoshinori TSUCHIYA, Hiroyuki TARUMI, Shinichi HOSHI, Masaki MATSUI, Kenji ITOH, Tetsuo NARITA, Tetsu KACHI
-
Publication number: 20160372587Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.Type: ApplicationFiled: August 28, 2014Publication date: December 22, 2016Inventors: Yoshinori TSUCHIYA, Shinichi HOSHI, Kazuyoshi TOMITA, Kenji ITOH, Masahito KODAMA, Tsutomu UESUGI
-
Patent number: 9202726Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.Type: GrantFiled: January 20, 2014Date of Patent: December 1, 2015Assignee: DENSO CORPORATIONInventors: Yoshinori Tsuchiya, Shinichi Hoshi, Masaki Matsui
-
Patent number: 9142661Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a first electrode, and a contact region. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The first electrode has a first and a second portion. The first portion is provided in a first direction and has a lower end being positioned below a lower end of the third semiconductor region. The second portion is in contact with the first portion and is provided on the third semiconductor region. The contact region is provided between the first portion and the second semiconductor region and is electrically connected to the first electrode and the second semiconductor region.Type: GrantFiled: September 12, 2013Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Takashi Shinohe
-
Patent number: 9105709Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H-SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C-SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.Type: GrantFiled: October 16, 2013Date of Patent: August 11, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Yoshinori Tsuchiya
-
Patent number: 8994034Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.Type: GrantFiled: February 24, 2012Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Yoshinori Tsuchiya, Takashi Shinohe
-
Publication number: 20140273482Abstract: A manufacturing method of a semiconductor device including arranging a compound semiconductor above a stage of a chamber, supplying an etching gas into the chamber, and generating a plasma in the chamber is provided. The compound semiconductor includes a group-III element nitride as a main component. A surface of the compound semiconductor is processed by a dry etching. Light is irradiated into the chamber during the generating of the plasma. A dry etching apparatus including a chamber including a stage, on which a compound semiconductor is mounted, and a light source irradiating light into the chamber is provided. The chamber is supplied with an etching gas. A plasma is generated in the chamber. A surface of the compound semiconductor is an object of a dry etching.Type: ApplicationFiled: January 20, 2014Publication date: September 18, 2014Applicant: DENSO CORPORATIONInventors: Yoshinori TSUCHIYA, Shinichi HOSHI, Masaki MATSUI
-
Patent number: 8790983Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.Type: GrantFiled: January 16, 2014Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Takashi Shinohe
-
Patent number: RE46271Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: GrantFiled: November 5, 2014Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
-
Patent number: RE47640Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: GrantFiled: January 5, 2017Date of Patent: October 8, 2019Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama