Abstract: A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor co

Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a first electrode, and a contact region. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The first electrode has a first and a second portion. The first portion is provided in a first direction and has a lower end being positioned below a lower end of the third semiconductor region. The second portion is in contact with the first portion and is provided on the third semiconductor region. The contact region is provided between the first portion and the second semiconductor region and is electrically connected to the first electrode and the second semiconductor region.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.

Abstract: A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor co

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.

Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.

Abstract: A method for manufacturing a semiconductor device according to the present embodiment includes the steps of forming a metallic silicide film on an n-type impurity region and a p-type impurity region made of silicon carbide (SiC), performing ion implantation of phosphorous (P) into the metallic silicide film on the n-type impurity region, performing a first thermal treatment, performing ion implantation of aluminum (Al) into the metallic silicide film on the p-type impurity region, and performing a second thermal treatment at a temperature lower than the first thermal treatment.

Abstract: A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.

Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.