Patents by Inventor Yoshinori Tsuchiya
Yoshinori Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8174080Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: GrantFiled: July 15, 2011Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
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Patent number: 8169040Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.Type: GrantFiled: June 28, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Tsuchiya, Masato Koyama, Masahiko Yoshiki
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Patent number: 8168499Abstract: It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si<31/12 above the first gate insulating film, and a second nickel silicide having a composition of Ni/Si?31/12 on the second gate insulating film; and segregating aluminum at an interface between the first nickel silicide and the first gate insulating film by diffusing aluminum through the first nickel silicide.Type: GrantFiled: April 23, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Seiji Inumiya
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Patent number: 8148787Abstract: There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.Type: GrantFiled: March 9, 2010Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Akira Nishiyama, Yoshinori Tsuchiya, Reika Ichihara
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Publication number: 20120061773Abstract: MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.Type: ApplicationFiled: September 14, 2010Publication date: March 15, 2012Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventor: Yoshinori Tsuchiya
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Patent number: 8129792Abstract: A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.Type: GrantFiled: September 18, 2008Date of Patent: March 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Hiroki Tanaka, Masahiko Yoshiki, Masato Koyama
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Publication number: 20120049281Abstract: According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.Type: ApplicationFiled: August 27, 2010Publication date: March 1, 2012Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Yoshinori Tsuchiya, Ryosuke Iijima, Atsushi Yagishita
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Patent number: 8120117Abstract: Gate electrode structures having a thin layer of ReO3 formed with high effective work function and high heat resistance are disclosed. The thin layer of ReO3 is formed by providing a semiconductor structure having an oxygen-containing metal alloy layer and a rhenium layer. A heat annealing step diffuses Re from the rhenium layer through the high-oxygen containing metal alloy layer to form a thin layer of ReO3.Type: GrantFiled: May 1, 2009Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshinori Tsuchiya
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Publication number: 20110275184Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: ApplicationFiled: July 15, 2011Publication date: November 10, 2011Inventors: Reika ICHIHARA, Yoshinori TSUCHIYA, Masato KOYAMA, Akira NISHIYAMA
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Patent number: 8053300Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: GrantFiled: August 20, 2007Date of Patent: November 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
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Publication number: 20110266632Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: ApplicationFiled: July 15, 2011Publication date: November 3, 2011Inventors: Reika ICHIHARA, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
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Patent number: 7986014Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.Type: GrantFiled: December 22, 2009Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama
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Patent number: 7977182Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.Type: GrantFiled: November 26, 2008Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshifumi Nishi, Yoshinori Tsuchiya, Takashi Yamauchi, Junji Koga
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Patent number: 7964489Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.Type: GrantFiled: June 25, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
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Patent number: 7902612Abstract: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.Type: GrantFiled: September 11, 2008Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga, Koichi Kato, Nobutoshi Aoki, Kazuya Ohuchi
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Patent number: 7863695Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.Type: GrantFiled: August 28, 2008Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masamichi Suzuki, Masato Koyama, Yoshinori Tsuchiya, Hirotaka Nishino, Reika Ichihara, Akira Takashima
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Publication number: 20100327364Abstract: A semiconductor device includes: a substrate and an n-channel MIS transistor. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, wherein a first source/drain region is formed in the p-type semiconductor region and separated from each other. The n-channel MIS transistor includes a first gate insulating film on the p-type semiconductor region between the first source/drain regions. The n-channel MIS transistor further includes a first gate electrode having a stack structure formed with a gate dielectric, a first metal layer and a first compound layer, the first metal layer having a thickness less than 2 nm and having a work function of 4.3 eV or smaller, the first metal layer being formed on the metallic layer having a work function larger than 4.4 eV and the first compound layer containing Al and a second metal that is different from the first metal.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventor: Yoshinori Tsuchiya
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Publication number: 20100276760Abstract: Gate electrode structures having a thin layer of ReO3 formed with high effective work function and high heat resistance are disclosed. The thin layer of ReO3 is formed by providing a semiconductor structure having an oxygen-containing metal alloy layer and a rhenium layer. A heat annealing step diffuses Re from the rhenium layer through the high-oxygen containing metal alloy layer to form a thin layer of ReO3.Type: ApplicationFiled: May 1, 2009Publication date: November 4, 2010Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventor: Yoshinori Tsuchiya
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Publication number: 20100258880Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.Type: ApplicationFiled: June 28, 2010Publication date: October 14, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshinori TSUCHIYA, Masato Koyama, Masahiko Yoshiki
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Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers
Patent number: 7807538Abstract: A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.Type: GrantFiled: September 11, 2007Date of Patent: October 5, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga