Patents by Inventor Yoshio Inoue

Yoshio Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7017134
    Abstract: An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: March 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Ken Saito, Yoshio Inoue, Koji Hirakimoto
  • Patent number: 6978431
    Abstract: A redundancy detection unit refers to layout data stored in a data storage unit and reflecting completed automatic placement and routing to detect a redundant region in a region having a cell arranged therein. An automatic insertion unit inserts in the detected redundant region a capacitive cell having a capacitive component and free of logic. As such a voltage drop can be reduced in a region scarce of LSI wiring resources. Furthermore, increased wiring capacitance can be provided without increased LSI chip area.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: December 20, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Koji Hirakimoto, Yoshio Inoue
  • Publication number: 20050246676
    Abstract: The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient ?, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S.
    Type: Application
    Filed: April 22, 2005
    Publication date: November 3, 2005
    Applicant: Renesas Technology Corp.
    Inventors: Toshiyuki Sadakane, Ken Saito, Yoshio Inoue
  • Patent number: 6938232
    Abstract: A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 30, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Ken Saito, Yoshio Inoue, Kazuhiro Takahashi, Koji Hirakimoto
  • Publication number: 20050020980
    Abstract: A pump system for an infusion system includes a linear drive (36, 36?) which minimizes the space occupied by the pump components in a portable housing (10, 10?). A motor (34) and a motor drive shaft (42) are arranged in parallel with, and adjacent to a syringe (14, 14?) and lead screw (94, 94?). A gear box (54) connects the drive shaft and lead screw to transfer rotational movements between them. A piston driving member, such as a drive nut (116) converts the rotational movement of the lead screw into linear motion of a syringe piston (24). A cap (190, 190?) couples the syringe (14, 14?) to the housing and provides an outlet for the liquid to be dispensed. In one embodiment, the cap (190?) is configured to rotate relative to the housing in one direction only, during locking. Rotational movement is also used for locking the piston (24) to the drive nut (116) against relative axial movement.
    Type: Application
    Filed: June 7, 2004
    Publication date: January 27, 2005
    Inventors: Yoshio Inoue, Kirk Ramey, Yoshiyuki Sonoda, Robert Sowell, Robert Williams
  • Patent number: 6844807
    Abstract: A home electronics system enabling rapid execution of remote control of controlled devices includes a home server, a cellular phone connected to the home server via a public line network, and devices to be controlled controlled in response to a signal from the home server. When the user selects via cellular phone an area, a state or a type of the devices to, the home server creates an image of the current state information showing the state of the devices for transmitting to the cellular phone.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshio Inoue, Shinichiro Ohashi
  • Publication number: 20040228167
    Abstract: An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.
    Type: Application
    Filed: May 3, 2004
    Publication date: November 18, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Ken Saito, Yoshio Inoue, Koji Hirakimoto
  • Patent number: 6704916
    Abstract: A method for optimizing placement and routing includes producing a net list constituting circuit connection information in a hardware description language, executing logic synthesis of the net list to output a gate-level net list with optimized logic, determining clusterings based on logic gap information used for optimizing the logic, outputting clustering information expressing a particular determination, and executing placement and routing based on the gate-level net list and the clustering information.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: March 9, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takeshi Nishida, Yoshio Inoue
  • Publication number: 20040031007
    Abstract: A redundancy detection unit refers to layout data stored in a data storage unit and reflecting completed automatic placement and routing to detect a redundant region in a region having a cell arranged therein. An automatic insertion unit inserts in the detected redundant region a capacitive cell having a capacitive component and free of logic. As such a voltage drop can be reduced in a region scarce of LSI wiring resources. Furthermore, increased wiring capacitance can be provided without increased LSI chip area.
    Type: Application
    Filed: February 27, 2003
    Publication date: February 12, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Koji Hirakimoto, Yoshio Inoue
  • Patent number: 6691271
    Abstract: A built-in self-test circuit including a signal generator and operational elements. The operational elements perform arithmetic operations on a test signal value A, generated by the signal generator, to obtain a comparison signal value A which is fundamentally equal to the test signal value A of the signal generator. By comparing the test signal value A with the comparison signal value A, a test result is obtained.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: February 10, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yusuke Kanehira, Toshinori Inoshita, Yoshio Inoue
  • Publication number: 20040001007
    Abstract: It is an object to automatically and rapidly assign a logical network address to a terminal connected newly to a network. A data holding section (14) of a network terminal (10) holds a value of a self-device address (DA) and information indicating whether the DA has a maximum value in the same network address (NA) or not. When a terminal connected newly to a network transmits address request data for requesting to give an address onto the network, a terminal having the maximum DA at that time transmits DA grant data indicative of a self-address (that is, the maximum DA) as an acknowledgement thereof. A new terminal receiving the DA grant data sets a greater value than the maximum DA to be the self-DA.
    Type: Application
    Filed: December 23, 2002
    Publication date: January 1, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshio Inoue, Takashi Hirosawa, Harufusa Kondoh
  • Publication number: 20030229874
    Abstract: A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.
    Type: Application
    Filed: December 17, 2002
    Publication date: December 11, 2003
    Inventors: Ken Saito, Yoshio Inoue, Kazuhiro Takahashi, Koji Hirakimoto
  • Patent number: 6654939
    Abstract: A scan flip flop with a selector is inserted into a position on a path where a timing error has occurred, based on timing analysis in a logic BIST mode, so that the path where the timing error has occurred is pipelined.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: November 25, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yu Yamamoto, Yoshio Inoue
  • Patent number: 6606730
    Abstract: Positions of the blocks on a semiconductor chip are decided. Then, positions of the block pins are provisionally decided based on the positions of the blocks. Subsequently cells are disposed within the blocks. Finally, the position of a block pin is changed to a position which is, for the block pin under consideration, based on the position of a cell that is to be connected to that block pin, of the cells disposed in the corresponding block.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: August 12, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyotake Yoshimaru, Yoshio Inoue
  • Patent number: 6570305
    Abstract: A silicon substrate is used as the substrate, on which a conical projection is formed as a cathode. A gate electrode is arranged via an insulating film formed on the substrate. The gate electrode is formed so as to enclose and encircle the cathode while the pointed portion of the cathode and the surface of the gate electrode are coated with two layered coating films.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: May 27, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Urayama, Keiichiro Uda, Seiki Yano, Yoshio Inoue
  • Patent number: 6525669
    Abstract: In a remote control system according to the present invention, a plurality of receivers are arranged for a network. Each receiver has an unique ID number. A control unit controls an operation of each receiver through the network. An input unit uses the unique ID number in each receiver for registration in the control unit. Thus, the control unit individually manages (controls) each receiver through the network. Thus, a plurality of receivers of the same type can be individually managed.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: February 25, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichiro Ohashi, Yoshio Inoue
  • Publication number: 20030023493
    Abstract: Merchandise information such as an expiration date, a price and the quantity of merchandise purchased by a purchaser is registered at a POS terminal at a store, and the merchandise information is recorded in an IC card by an IC card controller. At home, an IC card controller of a home server reads the merchandise information stored in the IC card and applies the same to a CPU. The CPU adds information of purchased merchandise to current inventory information for inventory management, sets the expiration date as an alarm time in a management table, and displays merchandise close on the expiration date onto a liquid crystal panel.
    Type: Application
    Filed: June 25, 2002
    Publication date: January 30, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichiro Ohashi, Yoshio Inoue
  • Publication number: 20020199161
    Abstract: A scan flip flop with a selector is inserted into a position on a path where a timing error has occurred based on timing analysis in a logic BIST mode, so that the path where the timing error has occurred is pipelined.
    Type: Application
    Filed: November 14, 2001
    Publication date: December 26, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yu Yamamoto, Yoshio Inoue
  • Patent number: 6472603
    Abstract: A weak current wire not susceptive to external electromagnetic waves, lightweight, having a relatively small outer diameter, and applicable to electromagnetic wave shield communication cables and non-underground communication cables not radiating electromagnetic waves externally, such as signal cables, control cables and wire harnesses.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: October 29, 2002
    Assignee: Tomoegawa Paper Co.
    Inventor: Yoshio Inoue
  • Publication number: 20010030597
    Abstract: A home electronics system enabling rapid execution of remote control of controlled devices includes a home server, a cellular phone connected to the home server via a public line network, and devices to be controlled controlled in response to a signal from the home server. When the user selects via cellular phone an area, a state or a type of the devices to, the home server creates an image of the current state information showing the state of the devices for transmitting to the cellular phone.
    Type: Application
    Filed: February 14, 2001
    Publication date: October 18, 2001
    Applicant: MITSUBUSHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshio Inoue, Shinichiro Ohashi