Patents by Inventor Yoshio Nishi

Yoshio Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4153487
    Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.
    Type: Grant
    Filed: August 5, 1977
    Date of Patent: May 8, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4151019
    Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.
    Type: Grant
    Filed: August 5, 1977
    Date of Patent: April 24, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4119998
    Abstract: An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.
    Type: Grant
    Filed: July 14, 1977
    Date of Patent: October 10, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4106049
    Abstract: A semiconductor device comprises a D.C. voltage supply region comprising a semiconductor substrate of one conductivity type having a first layer of high impurity concentration at least at its surface, and a second layer of low impurity concentration and of the same conductivity type as that of the D.C. voltage supply region, provided thereon and formed interiorly with a thin buried layer of the opposite conductivity type to that of the second layer at the vicinity of the D.C. voltage supply region. A grounding region of said opposite conductivity layer is provided in a manner to surround a specified region of the second layer and extend from the surface of the second layer to the buried layer, said surrounded specified region serving as a signal input region. In the surface of the signal input region, there is provided at least one signal output region constituting a diode together with the signal input region.
    Type: Grant
    Filed: February 22, 1977
    Date of Patent: August 8, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Satoshi Shinozaki, Yoshio Nishi, Yoshihisa Mizutani
  • Patent number: 4106045
    Abstract: A field effect transistor includes a thin silicon layer formed on a sapphire substrate and having source, gate and drain regions. A buried layer of the same conductivity type as that of the gate region and a higher impurity concentration than that of the gate region at the lower portion of a junction between the source and gate regions.
    Type: Grant
    Filed: May 14, 1976
    Date of Patent: August 8, 1978
    Assignee: The President of the Agency of Industrial Science and Technology
    Inventor: Yoshio Nishi
  • Patent number: 4064526
    Abstract: An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate.
    Type: Grant
    Filed: December 24, 1975
    Date of Patent: December 20, 1977
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4058419
    Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.
    Type: Grant
    Filed: December 24, 1975
    Date of Patent: November 15, 1977
    Assignee: Tokyo Shibaura Electric, Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4054900
    Abstract: An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.
    Type: Grant
    Filed: December 24, 1975
    Date of Patent: October 18, 1977
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
  • Patent number: 4019198
    Abstract: A non-volatile semiconductor memory device includes source and drain regions formed on a semiconductor substrate to define p-n junctions with the substrate and a gate layer having a silicon oxide film and a silicon nitride film. A high impurity concentration diffusion layers are formed around at least one of the source and drain regions, which have the same conductivity type as the substrate, an impurity concentration of above 10.sup.17 atoms cm.sup.-.sup.3 and a width of below 1 .mu.m.
    Type: Grant
    Filed: July 3, 1974
    Date of Patent: April 19, 1977
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Norio Endo, Yoshio Nishi
  • Patent number: 3932584
    Abstract: Hydrogen sulfide-containing waste gases whose complete treatment is indispensable from the viewpoint of environmental pollution problem, are purified in two steps consisting of a first step in which the gases are absorbed in an aqueous solution of sodium hydroxide or/and sodium sulfide, and a second step in which sulfuric acid and sulfur dioxide gas are simultaneously introduced into the resulting solution after absorption to deposit sulfur. Further, for recovery of the resulting sulfur, a particular apparatus is provided.
    Type: Grant
    Filed: January 25, 1974
    Date of Patent: January 13, 1976
    Assignee: Asahi Kasei Kogyo Kabushiki Kaisha
    Inventors: Tokuzo Asakusa, Taketoshi Honma, Isao Hirashita, Koichi Yasui, Yoshio Nishi, Koichi Murayama