Patents by Inventor Yoshio Ozawa
Yoshio Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240188307Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: February 14, 2024Publication date: June 6, 2024Applicant: Kioxia CorporationInventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
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Patent number: 11937437Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: July 21, 2021Date of Patent: March 19, 2024Assignee: Kioxia CorporationInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Publication number: 20210351235Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicant: Toshiba Memory CorporationInventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
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Patent number: 11101325Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: August 14, 2018Date of Patent: August 24, 2021Assignee: Toshiba Memory CorporationInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Patent number: 10968357Abstract: A transfer-printing ink contains a pigment and a fixing resin. The mass ratio of the pigment to the fixing resin is 1:1 to 1:5, and the ink has a viscosity of 3 mPas to 10 mPas at 23° C. The ink is ejected onto a transfer paper base by an ink-jet recording device when transfer paper is prepared. The ink is then transferred from the transfer paper to cloth as a result of the transfer paper, with the cloth laid over it, being heated.Type: GrantFiled: June 7, 2018Date of Patent: April 6, 2021Assignee: KYOCERA DOCUMENT SOLUTIONS INC.Inventor: Yoshio Ozawa
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Patent number: 10507643Abstract: A transfer-printing ink is ejected onto a transfer paper base on an ink-jet recording device when transfer paper is prepared, and is transferred from the transfer paper to cloth when the transfer paper with the cloth laid over it is heated. The ink contains a pigment, an anionic fixing resin, and a volatile amine as a neutralizer for neutralizing the fixing resin. The average particle diameter of the pigment is 30 nm to 150 nm. The pigment-to-fixing resin mass ratio is 1:1 to 1:5. The added amount of the volatile amine is 0.8 to 1.5 times the neutralization equivalent.Type: GrantFiled: June 1, 2018Date of Patent: December 17, 2019Assignee: KYOCERA Document Solutions Inc.Inventor: Yoshio Ozawa
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Publication number: 20190061401Abstract: Transfer paper for transfer printing has an image formed on its surface with a water-based transfer-printing ink containing a pigment and a fixing resin ejected from an ink-jet recording device, and is then, with cloth laid over it, heated so that the image is transferred to the cloth. The transfer paper has a base layer and a surface layer. The surface layer is composed of a hydrophilic ink reception layer laid on the base layer and a releasing layer forming agent containing an emulsion of hydrophobic particles having their surface coated with a hydrophilic emulsifier.Type: ApplicationFiled: July 26, 2018Publication date: February 28, 2019Applicant: KYOCERA Document Solutions Inc.Inventor: Yoshio OZAWA
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Publication number: 20190006419Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: August 14, 2018Publication date: January 3, 2019Applicant: Toshiba Memory CorporationInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Publication number: 20180362786Abstract: A transfer-printing ink contains a pigment and a fixing resin. The mass ratio of the pigment to the fixing resin is 1:1 to 1:5, and the ink has a viscosity of 3 mPas to 10 mPas at 23° C. The ink is ejected onto a transfer paper base by an ink-jet recording device when transfer paper is prepared. The ink is then transferred from the transfer paper to cloth as a result of the transfer paper, with the cloth laid over it, being heated.Type: ApplicationFiled: June 7, 2018Publication date: December 20, 2018Applicant: KYOCERA Document Solutions Inc.Inventor: Yoshio OZAWA
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Publication number: 20180362787Abstract: A transfer-printing ink is ejected onto a transfer paper base on an ink-jet recording device when transfer paper is prepared, and is transferred from the transfer paper to cloth when the transfer paper with the cloth laid over it is heated. The ink contains a pigment, an anionic fixing resin, and a volatile amine as a neutralizer for neutralizing the fixing resin. The average particle diameter of the pigment is 30 nm to 150 nm. The pigment-to-fixing resin mass ratio is 1:1 to 1:5. The added amount of the volatile amine is 0.8 to 1.5 times the neutralization equivalent.Type: ApplicationFiled: June 1, 2018Publication date: December 20, 2018Applicant: KYOCERA Document Solutions Inc.Inventor: Yoshio OZAWA
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Publication number: 20180361768Abstract: A transfer-printing method includes a transfer paper preparing step, a transferring step, and a releasing step. The transfer paper preparing step involves forming an image using transfer-printing ink containing a pigment and a fixing resin by ejecting the ink onto a transfer paper base and then drying at a temperature lower than the cross-linking temperature of the fixing resin to obtain transfer paper. The transferring step involves transferring the image formed on the transfer paper to cloth by pressing, while heating at a temperature higher than the cross-linking temperature of the fixing resin. The releasing step involves releasing the transfer paper from the cloth having the image fixed to it. The layer thickness of the ink layer formed on the transfer paper base is 50 nm to 500 nm, and, in the transferring step, the ink layer is transferred in the form of film to the surface of the cloth.Type: ApplicationFiled: June 1, 2018Publication date: December 20, 2018Applicant: KYOCERA Document Solutions Inc.Inventors: Yoshio OZAWA, Erika TANAKA
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Patent number: 10056433Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: August 8, 2016Date of Patent: August 21, 2018Assignee: Toshiba Memory CorporationInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Patent number: 9685607Abstract: A non-volatile semiconductor memory device according to an embodiment includes a plurality of first wiring lines that extend in a first direction, a plurality of second wiring lines that extend in a second direction intersecting the first direction to cross the first wiring lines, and memory cells, each of which is provided at a portion where the first wiring line crosses the second wiring line. The memory cell includes a variable resistance layer in the space between the wiring lines where the first wiring line crosses the second wiring line, a seam in the variable resistance layer extending in a direction between the first wiring layer and the second wiring layer, and a metal supply layer that comes in contact with the variable resistance layer and the seam.Type: GrantFiled: March 3, 2015Date of Patent: June 20, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yoshio Ozawa
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Patent number: 9547247Abstract: A toner includes a plurality of toner particles that each include a core and a shell layer disposed over a surface of the core. The shell layer contains a unit derived from a thermoplastic resin and a unit derived from a monomer or prepolymer of a thermosetting resin. A surface of each of the toner particles has a Young's modulus that changes by a proportion of no greater than 20% from 30° C. to 50° C., and changes by a proportion from 50° C. to 70° C. that when divided by the proportion of change from 30° C. to 50° C., yields a value of at least 3.0 and no greater than 10.0. The Young's modulus is measured in a state in which an external additive is not adhered to the toner particle using a scanning probe microscope while raising a cantilever temperature thereof.Type: GrantFiled: January 15, 2015Date of Patent: January 17, 2017Assignee: KYOCERA Document Solutions Inc.Inventors: Yoshio Ozawa, Noriaki Sakamoto, Ken Maetani
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Patent number: 9523939Abstract: A liquid developer contains an electrically insulating liquid carrier and toner particles dispersed in the liquid carrier. Each toner particle includes a core and a shell layer that is formed on a surface of the core and contains a thermosetting resin.Type: GrantFiled: July 25, 2014Date of Patent: December 20, 2016Assignee: KYOCERA Document Solutions Inc.Inventors: Hidetoshi Miyamoto, Katsuki Osanishi, Yoshio Ozawa
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Publication number: 20160351621Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: August 8, 2016Publication date: December 1, 2016Inventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
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Patent number: 9450181Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: May 27, 2014Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Patent number: 9417543Abstract: A toner includes toner particles each including a core and a shell layer disposed over a surface thereof. The shell layers contain a unit derived from a thermoplastic resin and a unit derived from a monomer or prepolymer of a thermosetting resin. Young's moduli of the shell layers and the cores, as measured using an SPM while raising cantilever temperature thereof, satisfy conditions: X2/X1 is at least 2.0 and no greater than 5.0; and Y2/Y1 is at least 4.0 and no greater than 7.0. X1 denotes a proportion of change of the Young's modulus of the shell layers and X2 denotes a proportion of change of the Young's modulus of the cores from 30° C. to 50° C. Y1 denotes a proportion of change of the Young's modulus of the shell layers and Y2 denotes a proportion of change of the Young's modulus of the cores from 50° C. to 70° C.Type: GrantFiled: January 20, 2015Date of Patent: August 16, 2016Assignee: KYOCERA Document Solutions Inc.Inventors: Yoshio Ozawa, Noriaki Sakamoto, Kazuki Tsuchihashi
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Patent number: 9406811Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.Type: GrantFiled: May 22, 2014Date of Patent: August 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
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Patent number: 9389526Abstract: An electrostatic latent image developing toner includes toner particles each including a toner core and a shell layer. The shell layer contains a resin including a unit derived from a monomer of a thermosetting resin and a unit derived from a thermoplastic resin. The thermosetting resin is one or more resins selected from the group of amino resins consisting of a melamine resin, a urea resin, and a glyoxal resin. When heat and pressure are applied to a toner layer formed on a polyester film under conditions of a temperature of 140° C. and a pressure of 7 MPa so that the toner particles are not superimposed, the toner particles of the toner layer are broken in a manner that a melt of a component of the toner core flows out from a plurality of points in an outer surface of the shell layer.Type: GrantFiled: July 7, 2014Date of Patent: July 12, 2016Assignee: KYOCERA Document Solutions Inc.Inventors: Yoshio Ozawa, Noriaki Sakamoto, Hiroaki Moriyama, Tomoyuki Ogawa, Takatoshi Nozaki