Patents by Inventor Yoshio Ozawa
Yoshio Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8373222Abstract: In a nonvolatile semiconductor memory device, a stacked body is provided on a silicon substrate by alternately stacking pluralities of isolation dielectric films and electrode films, a through-hole is formed in the stacked body to extend in the stacking direction, a memory film is formed by stacking a block layer, a charge layer and a tunnel layer in this order at an inner face of the through-hole, and thereby a silicon pillar is buried in the through-hole. At this time, the electrode film is protruded further than the isolation dielectric film toward the silicon pillar at the inner face of the through-hole, and an end face of the isolation dielectric film has a curved shape displacing toward the silicon pillar side as the electrode film is approached.Type: GrantFiled: August 19, 2009Date of Patent: February 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Yoshio Ozawa
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Patent number: 8354705Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.Type: GrantFiled: June 21, 2011Date of Patent: January 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Yoshio Ozawa
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Patent number: 8341970Abstract: An equipment control system includes a control device, and a control program in which present-round defrosting operation start time can be changed appropriately. An integrated controller controls a defrosting operation to remove frost adhered to showcases, in which the defrosting operation is started at a fixed or varying time interval. The integrated controller stores past record data based on required time for past defrosting operations for different environmental conditions. The integrated controller includes an environmental condition acquisition unit for obtaining present environmental conditions; a database control unit for obtaining required time for a present-round defrosting operation based on the past record data corresponding to the present environmental conditions from among the stored past record data; and a start time changing unit for changing start time of the present-round defrosting operation based on the obtained required time from the scheduled start time.Type: GrantFiled: February 27, 2009Date of Patent: January 1, 2013Assignee: SANYO Electric Co., Ltd.Inventors: Atsushi Ouchi, Yoshio Ozawa
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Patent number: 8330204Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.Type: GrantFiled: June 21, 2011Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Yoshio Ozawa
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Patent number: 8324679Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 26, 2012Date of Patent: December 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 8318561Abstract: According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other.Type: GrantFiled: November 4, 2011Date of Patent: November 27, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Publication number: 20120292587Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film.Type: ApplicationFiled: March 20, 2012Publication date: November 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kouji MATSUO, Noritake OHMACHI, Tomotaka ARIGA, Junichi WADA, Yoshio OZAWA
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Publication number: 20120282773Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.Type: ApplicationFiled: June 4, 2012Publication date: November 8, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Patent number: 8304352Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.Type: GrantFiled: March 18, 2011Date of Patent: November 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
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Publication number: 20120273863Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.Type: ApplicationFiled: July 11, 2012Publication date: November 1, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yoshio OZAWA, Fumiki AlSO
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Patent number: 8299571Abstract: According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resistance films.Type: GrantFiled: November 8, 2010Date of Patent: October 30, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Katsuyuki Sekine
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Patent number: 8294190Abstract: A semiconductor device including a semiconductor substrate, a tunnel insulation film provided on the surface of the semiconductor substrate, charge trap states at which an electron potential energy is higher than a Fermi level of the semiconductor substrate being provided at part of the tunnel insulation film at least in the vicinity of an interface with the semiconductor substrate, and at least one charge storage layer being provided on the tunnel insulation film, charges supplied from the semiconductor substrate via the tunnel insulation film being accumulated in the charge storage layer.Type: GrantFiled: May 10, 2010Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Patent number: 8278697Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: GrantFiled: January 17, 2012Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Patent number: 8278696Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having a higher oxygen concentration than the low oxygen concentration portions, a charge block insulating film formed on the charge storage insulating film, and control gate electrodes formed on the charge block insulating film and above the low oxygen concentration portions.Type: GrantFiled: April 16, 2009Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Ryota Fujitsuka
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Patent number: 8258565Abstract: There is provided a nonvolatile semiconductor memory device, including, a tunnel insulator, a floating gate electrode including a first floating gate electrode and a second floating gate electrode being constituted with a nondegenerate state semiconductor, an intergate insulating film formed to cover at least continuously an upper and a portion of a side surface of the floating gate electrode, and a control gate electrode in order, and an isolation insulating film, a lower portion of the isolation insulating film being embedded in the semiconductor substrate in both sides of the floating gate electrode along a channel width direction, an upper portion of the isolation insulating film contacting with a side surface of the first floating gate electrode and protruding to a level between an upper surface of the semiconductor substrate and an upper surface of the first floating gate electrode.Type: GrantFiled: December 17, 2009Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Patent number: 8253189Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: GrantFiled: July 28, 2009Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
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Patent number: 8254175Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region.Type: GrantFiled: December 15, 2009Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Hiroshi Matsuba, Yoshio Ozawa, Tetsuya Kai
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Patent number: 8247857Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.Type: GrantFiled: March 17, 2009Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Fumiki Aiso
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Publication number: 20120181598Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 8198159Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.Type: GrantFiled: March 24, 2008Date of Patent: June 12, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Yoshio Ozawa, Hirokazu Ishida, Katsuaki Natori, Seiji Inumiya