Abstract: A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges moved in and out of an internal portion of the charge storage layer via the tunnel insulating film is doped into a region of the charge storage layer on the interface side with the tunnel insulating film or a dopant is doped into the above region with higher concentration in comparison with that of another region.

Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Abstract: A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film.

Abstract: A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.

Abstract: A method of forming an insulating film includes forming a base film comprising a material whose surface is oxidized by being exposed to an oxidant. A source gas containing a metal material and a first oxidant having a first oxidation force are alternately supplied to form a first insulating film on the base film. A source gas containing a metal material and a second oxidant having a second oxidation force stronger than the first oxidation force are alternately supplied to form a second insulating film on the first insulating film.

Abstract: A semiconductor device including a gate dielectric film provided on at least one site on a surface of a semiconductor substrate, at least one first gate electrode provided on the gate dielectric film, an inter-electrode dielectric film provided while covering a surface of the first gate electrode, at least partial film thickness of a portion covering a portion other than a corner portion that does not come into contact with the gate dielectric film from among a plurality of corner portions of the first gate electrode being formed to be smaller than at least partial film thickness of a portion covering the corner portion that does not come into contact with the gate dielectric film, and a second gate electrode provided while covering a surface of the inter-electrode dielectric film.

Abstract: In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.

Abstract: A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

Abstract: A nonvolatile semiconductor memory device includes a first insulating film provided on a surface of a semiconductor substrate, a charge accumulation layer provided on the first insulating film, a second insulating film provided above the charge accumulation layer and contains silicon and nitrogen, a third insulating film provided on the second insulating film, and composed of a single-layer insulating film containing oxygen or a plural-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, relative dielectric constant thereof being larger than it of a silicon oxide film, a fourth insulating film provided on the third insulating film and contains silicon and nitrogen, a control gate provided above the fourth insulating film, and a fifth insulating film provided between the charge accumulation layer and the second insulating film or between the fourth insulating film and the control gate, and contains silicon and oxygen.

Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.

Abstract: A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

Abstract: A semiconductor memory device having a cell size of 60 nm or less includes a tunnel insulation film formed in a channel region of a silicon substrate containing a burying insulation film, a first conductive layer formed on the tunnel insulation film, an inter-electrode insulation film formed on the burying insulation film and the first conductive layer, a second conductive layer formed on the inter-electrode insulation film, a side wall insulation film formed on the side walls of the first conductive layer, the second conductive layer, and the inter-electrode insulation film, and an inter-layer insulation film formed on the side wall insulation film. The tunnel insulation film or the inter-electrode insulation film contains a high-dielectric insulation film. The side wall insulation film contains a predetermined concentration of carbon and nitrogen as well as chlorine having a concentration of 1×1019 atoms/cm3 or less.

Abstract: A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.

Abstract: A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a peripheral circuit which controls the memory cell array, the memory cell transistor including a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on the gate insulating film, a between-storage-layer-and-electrode insulating film which is provided on the floating gate electrode and through which the amount of passing charge is greater than that through the gate insulating film during the application of an electric field in write and erase operations of the semiconductor memory, and a control gate electrode on the between-storage-layer-and-electrode insulating film.

Abstract: A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating film, and side surfaces of a lower portion of the floating gate electrode, an inter-electrode insulating film which covers an upper surface and side surfaces of an upper portion of the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein upper corner portions of the floating gate electrode are rounded as viewed from a direction parallel with the upper surface and the side surfaces of the upper portion of the floating gate electrode.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.

Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.