Patents by Inventor Yoshiyuki Kaneko

Yoshiyuki Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7928952
    Abstract: An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Hajime Akimoto, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
  • Publication number: 20100244687
    Abstract: It is an object of the present invention to provide a plasma display panel with an improved panel structure for improving a discharge time-lag and, more particularly, to provide a plasma display panel with a new protective film structure, the plasma display panel having uniformed panel properties suitable for mass production with a high yield.
    Type: Application
    Filed: February 19, 2008
    Publication date: September 30, 2010
    Inventors: Yasuhito Yamaryo, Yoshiyuki Kaneko, Hiroyuki Tachihara, Takahiro Ueno, Takashi Kawasaki, Atsuo Ohtomi
  • Publication number: 20100213839
    Abstract: To provide a plasma display panel of improving a discharge time-lag. A plasma display panel of the present invention is characterized in that it comprises a pair of substrate assemblies opposed to each other sandwiching discharge spaces formed to seal a discharge gas therein, wherein one of the pair of substrate assemblies comprises: display electrodes arranged on a substrate; a dielectric layer for covering the display electrodes; and a protective layer for covering the dielectric layer, and the protective layer is configured so that a plurality of MgO single crystals are adhered to an MgO film in such a manner that crystal orientations of the plurality of MgO single crystals are aligned in one direction.
    Type: Application
    Filed: August 10, 2007
    Publication date: August 26, 2010
    Applicant: HITACHI, LTD.
    Inventors: Yasuhito Yamaryo, Yoshiyuki Kaneko, Takahiko Ueno, Hiroyuki Tachihara, Atsuo Ohtomi
  • Patent number: 7781962
    Abstract: Light-emitting devices (24) and light-emitting displays (1) for realizing bright display by allowing light emitted from an emissive layer (100) to efficiently contribute to a display. Polarization separators (500) are arranged between the emissive layer (100) and a phase plate (700). In the light of a wavelength range which includes a part or all of a light-emission wavelength range of the emissive layer and is narrower than a visible wavelength range and is directed from the emissive layer side to the polarization separators side, the polarization separators (500) reflect circularly polarized light components which are converted into linearly polarized light that is absorbed by the polarizer (600) due to the operation of the phase plate and transmit the other light.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 24, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masaya Adachi, Yoshiyuki Kaneko, Sukekazu Aratani, Shingo Ishihara
  • Patent number: 7696686
    Abstract: To provide an image display device including a lower electrode, an upper electrode, and an electron acceleration layer composed of an insulator or a semiconductor provided there between, and further including a thin film electron source array that emits electrons from the upper electrode, and a phosphor surface, wherein degradation of an electron emission characteristic caused by an increase of a work function due to an adhesive material to the above-described upper electrode is suppressed. An amount of S content adhering to the upper electrode is set equal to or less than 20 mol % of a total amount of elements used as the upper electrode in terms of elements by using an element belonging to Group VIII or Group Ib or a laminated film or alloy film thereof as a component of the upper electrode of the thin film electron source.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: April 13, 2010
    Assignee: Hitachi Displays, Ltd.
    Inventors: Masato Kaneeda, Yoshiyuki Kaneko, Tsutomu Kuniyasu, Yuuichi Kijima, Kenji Kato, Toshiaki Kusunoki
  • Publication number: 20100078690
    Abstract: As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.
    Type: Application
    Filed: September 12, 2009
    Publication date: April 1, 2010
    Inventors: Masao SUGIYAMA, Yoshiyuki KANEKO, Yoshinori KONDO, Masayoshi HIRASAWA
  • Patent number: 7633094
    Abstract: The present invention provides the following methods and displays. A method for manufacturing an EL display panel, having the step of forming a light-emitting layer by irradiating light on a photothermal conversion layer through a transparent base member while a dye layer of a transfer member having the transparent base member, the photothermal conversion layer and this fluorescent dye layer is kept in close contact with an object to which the dye is to be transferred, the transparent base member, the photothermal conversion layer and the transfer member being laminated in this order, so that the dye can be transferred to the object. An EL display panel produced according to this method, an image display having this panel, and a method for manufacturing the image display.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: December 15, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Sukekazu Aratani, Yoshiyuki Kaneko, Makoto Tsumura
  • Publication number: 20090201273
    Abstract: A display module includes a substrate. The substrate has a plurality of pixels, a signal line, a current supply line, and a data driving circuit. The pixel includes an emitting device and an active device, wherein the emitting device include a first electrode layer, an organic emitting layer formed on the first electrode layer, and a second electrode layer formed on the organic emitting layer, and the data driving circuit is disposed between a display area and a first side of the substrate on which an external terminal is placed. A third electrode layer is provided within a sealing area disposed between the display area and a second side of the substrate, and on a layer below the passivation film, and the second electrode layer is connected to the third electrode layer through a plurality of contact holes formed above the third electrode layer.
    Type: Application
    Filed: April 20, 2009
    Publication date: August 13, 2009
    Inventors: Toshihiro Sato, Yoshiyuki Kaneko
  • Publication number: 20090179247
    Abstract: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 16, 2009
    Inventors: Masako FUJII, Shigeki Obayashi, Naozumi Morino, Atsushi Hiraiwa, Shinichi Watarai, Takeshi Yoshida, Kazutoshi Oku, Masao Sugiyama, Yoshinori Kondo, Yuichi Egawa, Yoshiyuki Kaneko
  • Publication number: 20090153449
    Abstract: A display device including: a display portion with gate lines to which scanning signals are fed, a plurality of data lines to which picture image signals are fed, wherein the gate lines and data lines are crossed with each other in a matrix shape, TFTs and OLED elements disposed in regions surrounded by the gate lines and data lines; a scanning line driving circuit which feeds the scanning signals for the gate lines; a data line driving circuit which feeds the picture image signals for the data lines; a display control controller which provides timing control signals to the scanning line driving circuit and the data line driving circuit and further provides the picture image signals to the data line driving circuit; a timing regulation circuit which regulates the timing (clock frequency) of the timing control signals; and a picture image memory which stores the picture image signals.
    Type: Application
    Filed: January 26, 2009
    Publication date: June 18, 2009
    Inventors: Yoshiyuki Kaneko, Sukekazu Aratani
  • Patent number: 7525525
    Abstract: A display module includes an emitting device provided with a first electrode layer that is driven by an active device, an organic emitting layer that is coated on said first electrode layer, and a second electrode layer CD that is formed over said organic emitting layer. An electrode layer CNTB is provided on the substrate thereof lower than the second electrode layer CD and is coated with an insulating or passivation film. The electrode layer CNTB is in contact with the second electrode layer CD through a contact hole CNT.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: April 28, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Sato, Yoshiyuki Kaneko
  • Publication number: 20090106069
    Abstract: A counter management apparatus of the present invention issues a numbered ticket based on an input operation made by a customer and calls a customer to a counter, and includes: an input unit that receives an input of authentication information on a counter clerk who performs a predetermined transaction at the counter and an input of counter information associated with the counter; a specification unit that, based on the authentication information received by the input unit, specifies a transaction that can be handled by the counter clerk from a database in which the authentication information of the counter clerk and the transaction that can be handled by the counter clerk are associated and registered; and a counter information registration unit in which the transaction specified by the specification unit the counter information are associated and registered.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 23, 2009
    Inventors: Mitsutaka Asakura, Yoshiyuki Kaneko, Takashi Kimura
  • Patent number: 7501751
    Abstract: The present invention ensures the hermetic bonding of a support body which is interposed between a face substrate and a back substrate and is formed of a plurality of members thus easily realizing the large-sizing of a screen of a display image and, at the same time, enhancing a hermetic property holding function of the image display device. A support body is interposed between a face substrate and a back substrate while surrounding a display region and hermetically seals both substrates using a sealing material. The support body is formed by hermetically bonding a plurality of support body members each other using a bonding material which has a softening point higher than a softening point of the sealing material.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 10, 2009
    Assignee: Hitachi Displays, Ltd.
    Inventors: Yuuichi Kijima, Yoshiyuki Kaneko, Shigemi Hirasawa
  • Patent number: 7491972
    Abstract: A semiconductor device and a method of manufacture thereof by forming an amorphous semiconductor film on the surface of an insulative substrate, and irradiating the amorphous semiconductor film with a laser beam to crystallize it to form a polycrystalline semiconductor thin film. A transistor is then formed in the polycrystalline semiconductor thin film. More specifically, a UV-ray is irradiated to the rear face of the insulative substrate or the amorphous semiconductor film to heat the amorphous semiconductor film to a melting temperature or lower. Then a laser beam at a suitable shape selection laser energy density Ec forms the crystal grains with the number of closest crystal grains of 6 most predominantly being irradiated to convert the amorphous semiconductor film into a polycrystalline semiconductor thin film. The thin film transistor formed in this structure has a high yield and is capable of high-speed operation.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: February 17, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Takahiro Kamo, Yoshiyuki Kaneko
  • Patent number: 7483002
    Abstract: Pixels in a picture image display device are driven in such a manner that while introducing light, a quenching period is initiated in which electro optical elements in the pixels are quenched after scanning a plurality of gate lines for displaying one picture image. In other words, the pixels are driven while interposing the light quenching period in which the electro optical elements are quenched between one frame and a subsequent frame. Thereby, the phenomenon of blurred edges at the time of motion picture display, when the pixels including the electro optical elements are driven through an active matrix drive circuit, is suppressed and the picture quality of the picture image display device is improved.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: January 27, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiyuki Kaneko, Sukekazu Aratani
  • Publication number: 20080316192
    Abstract: An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 25, 2008
    Inventors: Hajime AKIMOTO, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
  • Patent number: 7434532
    Abstract: A small planning boat includes a filler opening for a fuel tank and an opening section that are formed on the deck of the boat body. The filler opening and the opening section are covered with a hatch cover when the hatch cover is closed. A fuel-receiving concave section is formed around the filler opening, so that the filler opening is positioned at the bottom surface section of a fuel-receiving concave section. A guide groove that declines downward from the bottom surface section on an outer side of the boat body can be formed as one piece with the fuel-receiving concave section. A storage section can also be formed inside the opening section. In addition, the filler opening can be positioned on the starboard side rearward from the opening section, and the guide groove can be formed in a section on an outer side of the opening section.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: October 14, 2008
    Assignee: Yamaha Marine Kabushiki Kaisha
    Inventor: Yoshiyuki Kaneko
  • Patent number: 7430466
    Abstract: A watercraft has steering force detection sections. Each steering force detection section includes a pressure receiving section. The pressure receiving sections are spaced from each other and are in the vicinity of a steering shaft. A pressing member is coupled to the steering shaft. The pressing member can press on at least one of the pressure receiving sections when the steering handlebars are rotated to a maximum steering angle. A received pressure detection section detects the pressure applied to the pressure receiving section. The pressure receiving section and the received pressure detection section are coaxially mounted in a pressure receiving section casing and a detection section casing. A guide tube can engage the pressure receiving section and the received pressure detection section. The guide tube is formed with ribs and grooves. The pressure receiving section has a pressure receiving member, a bolt, a plain washer, and a spring member.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 30, 2008
    Assignees: Yamaha Marine Kabushiki Kaisha, Yamaha Motor Co., Ltd.
    Inventors: Yoshiyuki Kaneko, Tomoyoshi Koyanagi, Yoshinori Harada, Yutaka Mizuno
  • Patent number: 7423623
    Abstract: An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: September 9, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hajime Akimoto, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
  • Patent number: 7417608
    Abstract: An organic LED (OLED) display device and an operating method of driving the same. In an OLED image display device, one switch transistor is provided in one pixel. For at least a part of an OFF period of time of the switch transistor, the OLED is in the non-light emission state, and also the bias of the polarity reverse to that in the light emission is applied to the OLED.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiyuki Kaneko, Takayuki Ouchi, Nobuaki Kabuto, Toshihiro Sato