Patents by Inventor Yoshiyuki Wada

Yoshiyuki Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7966721
    Abstract: In order to mount an electronic component, a connection terminal of the electronic component is bonded to electrodes of a substrate. This is done by using solder paste which mixes solder particles in a thermosetting adhesive. The solder paste is supplied to the electrodes and a recess. Solder print parts are formed. The electronic component is mounted and the connection terminal and the main body of the electronic component are adhered to the solder print parts, and are heated in this state by reflow. As a result, the connection terminal and the electrodes are bonded by a solder junction.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Publication number: 20100266049
    Abstract: An image decoding apparatus pertaining to the present invention includes a plurality of decoders. The image decoding apparatus (i) divides image data to decode into a plurality of pieces of partial data, (ii) acquires attribute information pieces each affecting decoding processing time of a corresponding one of the plurality of pieces of partial data, (iii) determines which of the plurality of decoders is caused to decode which of the plurality of pieces of partial data based on the attribute information pieces on the plurality of pieces of partial data and (iv) causes two or more of the plurality of decoders to decode two or more corresponding pieces of the partial data in parallel.
    Type: Application
    Filed: May 23, 2007
    Publication date: October 21, 2010
    Inventors: Takashi Hashimoto, Yoshiyuki Wada
  • Publication number: 20100206621
    Abstract: A wiring board with a built-in component includes an insulating board, a first wiring pattern on an upper surface of the insulating board, plural electrodes on the upper surface of the insulating board, a solder resist on the upper surface of the insulating board, plural solders on the electrodes, respectively, an electronic component joined to the electrodes with the solders, a sealing resin provided between the insulating board and the electronic component, a component-fixing layer provided on the upper surface of the insulating board and the first wiring pattern and having an insulating property, a second wiring pattern on the component-fixing layer, and an interlayer wiring connecting the first wiring pattern to the second wiring pattern. The solder resist surrounds the electrodes. The sealing resin entirely covers the solders and the solder resist. This wiring board can be efficiently manufactured by simple processes.
    Type: Application
    Filed: October 6, 2008
    Publication date: August 19, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Yoshiyuki Wada
  • Patent number: 7728745
    Abstract: A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuya Shigenobu, Yoshiyuki Wada, Satoshi Yamaguchi, Kozo Kimura, Takeshi Furuta
  • Publication number: 20100091842
    Abstract: A plurality of macroblocks constituting coded data are inverse quantized using a first quantization matrix that is used when coding a picture, to obtain a plurality of sets of coefficient data. The first quantization matrix is converted to a second quantization matrix using a first conversion value and a second conversion value, where the first conversion value is for converting a low frequency coefficient corresponding to a frequency lower than a predetermined frequency among a plurality of coefficients shown by the first quantization matrix, and the second conversion value is for converting a high frequency coefficient among the plurality of coefficients and is larger than the first conversion value (Step S408). When the second quantization matrix is a matrix for increasing a coding rate of the coded data, a converted scale is calculated by multiplying a quantization scale corresponding to at least one macroblock by ?1 (?1).
    Type: Application
    Filed: October 16, 2008
    Publication date: April 15, 2010
    Inventors: Hiroshi Ikeda, Yoshiyuki Wada
  • Publication number: 20100089628
    Abstract: A core layer has on its front surface a pair of connecting electrodes forming a wiring pattern and a resist formed between the pair of electrodes; an electronic component having a pair of connecting terminals; a solder part joining between electrodes and connecting terminals; and a sealing resin part filling a gap between the bottom surface of the electronic component and the front surface of the core layer and covering the resist and the solder part, to prevent a defect of a component built-in printed circuit substrate.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 15, 2010
    Applicant: Panasonic Corporation
    Inventors: Yoshiyuki WADA, Tadahiko SAKAI
  • Publication number: 20100000773
    Abstract: The invention intends to provide an electronic component mounting structure where the repairability and the impact resistance are combined. In an electronic component mounting structure, a plurality of solder balls disposed in plane between an electronic component and a substrate is melted to bond the electronic component and the substrate and a resin of which tensile elongation after the curing is in the range of 5 to 40% is filled in portions that are gaps between the electronic component and the substrate and correspond to at least four comers of the electronic component to reinforce. Since the reinforcement area is small, the repairability such as the easy removability of the resin and the reusability of the substrate are excellent, the resin itself is allowed to expand to the impact at the drop to play a role of reinforcing the bonding without breaking, and the impact resistance is excellent as well.
    Type: Application
    Filed: September 21, 2007
    Publication date: January 7, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Seiichi Yoshinaga, Yoshiyuki Wada, Tadahiko Sakai
  • Publication number: 20090047534
    Abstract: To provide a components joining method and a components joining structure which can realize joining of components while securing conduction at a low electrical resistance with high reliability. In a construction in which by using a solder paste containing solder particles 5 in a thermosetting resin 3a, a rigid substrate 1 and a flexible substrate 7 are bonded by the thermosetting resin 3a, and a first terminal 2 and a second terminal 8 are electrically connected by the solder particles 5, a blending ratio of an activator of the thermosetting resin 3a in the solder paste is properly set and oxide film removed portions 2b, 8b, and 5b are partially formed in oxide films 2a, 8a, and 5a of the first terminal 2, the second terminal 8, and the solder particles 5.
    Type: Application
    Filed: April 3, 2007
    Publication date: February 19, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tadahiko Sakai, Hideki Eifuku, Yoshiyuki Wada
  • Patent number: 7446423
    Abstract: In a semiconductor device provided with a thinned semiconductor element, the present invention intends to inhibit damage of the semiconductor element in the neighborhood of its outer periphery so as to improve reliability. A plurality of external connection terminals are formed on a front surface of the thinned semiconductor element. A plate higher in rigidity than the semiconductor element is adhered with a resin binder to a rear surface of the semiconductor element. An outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: November 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadahiko Sakai, Mitsuru Ozono, Yoshiyuki Wada
  • Publication number: 20080266147
    Abstract: A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the
    Type: Application
    Filed: April 23, 2008
    Publication date: October 30, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuya SHIGENOBU, Yoshiyuki WADA, Satoshi YAMAGUCHI, Kozo KIMURA, Takeshi FURUTA
  • Publication number: 20080260025
    Abstract: A coding rate converting apparatus according to the present invention re-quantizes first quantized data with a first quantization step size, using a second quantization step size larger than the first quantization step size, and includes: an inverse quantization unit generating orthogonal transform coefficients by inversely quantizing the first quantized data for each of unit blocks; a quantization unit generating second quantized data by quantizing the orthogonal transform coefficients using the second quantization step size; a filter intensity change judging unit judging whether a second filter intensity determined based on the second quantized data is changed from a first filter intensity determined based on the first quantized data; and a coefficient correcting unit generating, in the case of the second filter intensity, third quantized data by correcting the second quantized data so that a third filter intensity determined based on the third quantized data becomes equal to the first filter intensity.
    Type: Application
    Filed: April 15, 2008
    Publication date: October 23, 2008
    Inventor: Yoshiyuki Wada
  • Publication number: 20070221711
    Abstract: A method of packaging an electronic component, which is capable of enhancing electrical and mechanical bonding reliability of the electronic component. Terminal (4) is provided on the side face of electronic component (1). Electrode (6) is formed on one or the other major surface of substrate (5) and terminal (4) provided in electronic component (1) is located on electrode (6). Solder paste produced by mixing solder particles with thermosetting flux is applied to electrode (6), terminal (4) of electronic component (1) is mounted on and brought into contact with the applied solder paste, and electronic component (1) is mounted on substrate (5) with clearance (S) provided between a part of electronic component (1) and opposing substrate (5). Solder bonding structure (8) for coupling terminal (4) and electrode (6) is formed by reflow. Solder bonding structure (8) includes solder bonding portion (8a), resin reinforcing portion (8b) and resin adhering portion (8c).
    Type: Application
    Filed: October 12, 2005
    Publication date: September 27, 2007
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Publication number: 20070175969
    Abstract: In order to mount an electronic component, a connection terminal of the electronic component is bonded to electrodes of a substrate. This is done by using solder paste which mixes solder particles in a thermosetting adhesive. The solder paste is supplied to the electrodes and a recess. Solder print parts are formed. The electronic component is mounted and the connection terminal and the main body of the electronic component are adhered to the solder print parts, and are heated in this state by reflow. As a result, the connection terminal and the electrodes are bonded by a solder junction.
    Type: Application
    Filed: December 21, 2005
    Publication date: August 2, 2007
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Patent number: 7228064
    Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda
  • Patent number: 7071577
    Abstract: In a semiconductor device of a structure comprising a thin semiconductor element bonded to a reinforcing plate via a bonding layer of a predetermined thickness, resin binder used for forming the bonding layer contains fillers including a first filler, which has a diameter generally equal to a target thickness of the bonding layer to be adjusted to a value within a range of proper thickness (from 25 ?m to 200 ?m). This can maintain the bonding layer within the range of proper thickness when the semiconductor element is bonded to the plate, and ensure on-board mounting reliability of the semiconductor device.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: July 4, 2006
    Assignee: Matshushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Wada, Tadahiko Sakai
  • Publication number: 20060043543
    Abstract: There is provided a solder composition which contains: (1) a metal material comprising solder particles, and (2) a thermosetting flux material comprising a thermosetting resin and a solid resin which changes to be in its liquid-like state when heated with a proviso that the thermosetting resin is excluded from the solid resin, wherein a temperature at which the solid resin changes to be in the liquid-like state is lower than a temperature at which the thermosetting resin starts to cure.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Yoshiyuki Wada, Tadahiko Sakai, Seiichi Yoshinaga
  • Publication number: 20060043597
    Abstract: There is provided a solder composition which contains: (1) a metal material comprising solder particles, and (2) a thermosetting flux material comprising a thermosetting resin and a solid resin which transforms to its liquid-like state when heated with a proviso that the thermosetting resin is excluded from the solid resin.
    Type: Application
    Filed: August 24, 2005
    Publication date: March 2, 2006
    Inventors: Yoshiyuki Wada, Tadahiko Sakai, Seiichi Yoshinaga
  • Publication number: 20050116323
    Abstract: In a semiconductor device provided with a thinned semiconductor element, the present invention intends to provide a semiconductor device in which a damage of a semiconductor element is inhibited from occurring in the neighborhood of an outer periphery and thereby the reliability can be secured. In order to realize the object, the invention relates to a semiconductor device in which to a rear surface of a thinned semiconductor element on a front surface of which a plurality of external connection terminals is formed, a plate higher in the rigidity than the semiconductor element is adhered with a resin binder, wherein an outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.
    Type: Application
    Filed: April 14, 2003
    Publication date: June 2, 2005
    Inventors: Tadahiko Sakai, Mitsuru Ozono, Yoshiyuki Wada
  • Publication number: 20050053290
    Abstract: A decoding apparatus lightens the load incurred by padding processing. When the decoding apparatus outputs decoded data to a frame memory, a padding unit in the decoding apparatus judges whether the decoded data includes boundary pixels, and when boundary pixels are judged to be included, performs padding processing to an extension area using boundary pixel data. As a result, as well as pixels in one decoded macroblock being output, when boundary pixels are included in the output macroblock, the boundary pixels are output to the extension area. This eliminates the need to re-read the boundary pixels from the frame memory.
    Type: Application
    Filed: July 21, 2004
    Publication date: March 10, 2005
    Inventors: Yoshiyuki Wada, Kosuke Yoshioka, Hideshi Nishida
  • Publication number: 20040080047
    Abstract: In a semiconductor device of a structure comprising a thin semiconductor element bonded to a reinforcing plate with a bonding layer of a predetermined thickness, resin binder used for forming the bonding layer contains fillers including first filler, which has a diameter generally equal to a target thickness of the bonding layer to be adjusted to a value within a range of proper thickness (from 25 &mgr;m to 200 &mgr;m). This can maintain the bonding layer within the range of proper thickness when the semiconductor element is bonded to the plate, and ensure on-board mounting reliability of the semiconductor device.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Yoshiyuki Wada, Tadahiko Sakai