Patents by Inventor Yoshiyuki Wada

Yoshiyuki Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6617675
    Abstract: A semiconductor device assembly and a semiconductor device are provided which both can ensure reliability after a mounting process. The semiconductor device includes a semiconductor element equipped with bumps on an electrode patterned surface thereof for external connection. In the semiconductor device mounted on a substrate in the semiconductor device assembly, a semiconductor element shaped to have a thickness ranging from 200 &mgr;m to 10 &mgr;m has reduced flexural rigidity so as to be easily deflected. In the status that the bumps are joined to corresponding circuitry electrodes on the substrate, the semiconductor element can deflect at other portions other than its surface between two adjacent bumps according to contraction and distortion of the substrate. This allows the bumps to be dislocated in a direction parallel to a surface of the semiconductor element, hence relieving stress developed by the contraction of the substrate at the joint positions between the bumps and the circuitry electrodes.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: September 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadahiko Sakai, Mitsuru Ozono, Shoji Sakemi, Yoshiyuki Wada
  • Publication number: 20030026487
    Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 6, 2003
    Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda
  • Publication number: 20020084470
    Abstract: A semiconductor device assembly and a semiconductor device are provided which both can ensure reliability after a mounting process. The semiconductor device includes a semiconductor element equipped with bumps on an electrode patterned surface thereof for external connection. In the semiconductor device mounted on a substrate in the semiconductor device assembly, a semiconductor element shaped to have a thickness ranging 200 &mgr;m to 10 &mgr;m has reduced flexural rigidity so as to be easily deflected. In the status that the bumps are joined to corresponding circuitry electrodes on the substrate, the semiconductor element can deflect at other portion than its surface between two adjacent bumps according to contraction and distortion of the substrate. This allows the bumps to be dislocated in a parallel direction with a surface of the semiconductor element, hence relieving a stress developed by the contraction of the substrate at the joint positions between the bumps and the circuitry electrodes.
    Type: Application
    Filed: December 12, 2001
    Publication date: July 4, 2002
    Inventors: Tadahiko Sakai, Mitsuru Ozono, Shoji Sakemi, Yoshiyuki Wada
  • Patent number: 5505366
    Abstract: The present invention relates to a method for mounting electronic devices on a substrate by using soldering with flux which contains materials capable of ion-exchanging or ion-catching so as to catch impurity ions which seep from a solder portions, and thereby it is not necessary to have a fusing step and a cleaning step in an plating process of the method.
    Type: Grant
    Filed: June 20, 1994
    Date of Patent: April 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Nishi, Yoshiyuki Wada, Eigo Kadokami, Seiichi Yoshinaga
  • Patent number: 5489750
    Abstract: A method of mounting an electronic part with bumps on a circuit board is disclosed which enables bumps to be bonded to electrodes of the circuit board with certainty and which enables the judgement of the quality of bonding with precision. By making an area of the electrodes of the circuit board larger than those of the electrodes of the electronic part, the bumps heated and molten in the reflow soldering are spread over the electrodes of the circuit board to make its vertical cross-sectional configuration in a trapezoidal form. Therefore, the height dispersion of the bumps and the curvature of the circuit board are effectively absorbed whereby all the bumps can be bonded to the electrodes of the circuit board. Further, by measuring the planar area of the bumps, the judgement of the quality of bonding can be made with precision.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: February 6, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoji Sakemi, Yoshiyuki Wada
  • Patent number: 5289508
    Abstract: A clock information transmitting device coupled to a digital processing circuit which receives a transmission signal and generates a coded transmission signal includes a PLL circuit for generating a first signal and a sampling clock signal, both being synchronized with a synchronizing signal in the transmission signal. The sampling clock signal is used in the digital processing circuit. A clock information generating part counts pulses of a transmission clock signal and generates clock information indicating a number of pulses of a transmission clock signal in response to one of the synchronizing signal and the first signal generated by the PLL circuit. A multiplexer outputs a multiplexed signal including the clock information and the coded transmission signal to a transmission path.
    Type: Grant
    Filed: November 13, 1991
    Date of Patent: February 22, 1994
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Wada, Toshihiro Yamanaka
  • Patent number: 5278651
    Abstract: An apparatus which receives a high definition television (HDTV) signal having a plurality of signal components, delays a reference signal component which is one of the plurality of signal components and synchronizes respective phases of the plurality of signal components with the phase of the reference signal component.
    Type: Grant
    Filed: May 28, 1991
    Date of Patent: January 11, 1994
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Wada, Hiroaki Kawasumi
  • Patent number: 4960089
    Abstract: A fuel supply/ignition device for use with a stratified combustion system includes a fuel chamber formed adjacent to a combustion chamber. The fuel chamber is provided with a valve for supplying a liquid fuel and a spark plug for generating a spark. The spark plug is connected to a high-energy generator. When the liquid fuel is charged into the fuel chamber, and a high-energy discharge is generated by the spark plug, the liquid fuel in the fuel chamber is atomized to be sprayed into the combustion chamber, and is simultaneously ignited to provide stratified combustion. Application of the fuel supply/ignition device to an internal combustion engine contributes to a reduction in harmful components such as HC and NOx in an exhaust gas.
    Type: Grant
    Filed: November 20, 1989
    Date of Patent: October 2, 1990
    Assignee: Aisan Kogyo Kabushiki Kaisha
    Inventors: Michikata Kono, Yoshiyuki Wada, Tetuya Kamihara, Masahito Tatematsu, Koichi Suda