Patents by Inventor Yosuke Takeuchi

Yosuke Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210213762
    Abstract: A recording device includes a main body including a recording unit configured to perform recording on a medium pulled out from a roll body including the medium wound around a core member, and a leg part configured to support the main body from an installation surface on which the main body is installed. The leg part includes contact parts configured to make contact with the installation surface at respective positions different from each other. The contact parts include three reference contact parts located on a same plane and one movable contact part. The movable contact part is coupled with the main body through an elastic member that is elastically deformable in a direction that intersects the plane.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 15, 2021
    Inventors: Keiichi Yato, Yosuke Nakano, Atsuhiko Takeuchi
  • Patent number: 10424860
    Abstract: Example implementations involve an electrical connector and a test method of the electrical connector, wherein the electrical conduction condition between a ground member and a ground terminal can be easily confirmed while reliably contacting the ground member and ground terminal. Electrical connector involves a plurality of terminals including two types of terminals, namely, signal terminals and ground terminals; a retaining body, made of an insulating material, that arranges and retains the plurality of terminals in a condition where the signal terminals and ground terminals are intermingled; and a ground member retained by the retaining body on the inward side of the retaining body, in a condition contacting at least two ground terminals; wherein the ground member has a detecting part exposed from the retaining body in order to detect an electrical conduction condition between the ground terminals and the ground member.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: September 24, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Takeshi Okuyama, Yosuke Takeuchi
  • Patent number: 10283913
    Abstract: An electrical connector with a shielding plate in which signal terminals and ground terminals supported by insulating members are arranged in an intermixed order, signal terminals have at least a portion in the longitudinal direction thereof covered by a shielding plate, and respective contact portions formed in free end portions at the front ends of the signal terminals and ground terminals are subject to contact pressure applied by the corresponding counterpart terminals to one side of said contact portions, thereby resulting in resilient flexure, wherein in the shielding plate, at positions corresponding to the ground terminals in the direction of terminal array, there are provided grounding strips parallel to said ground terminals, said grounding strips extend forward and, at least in a state of contact between the ground terminals and counterpart terminals, the other side of the ground terminals is in contact with and supported by the grounding strips.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 7, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventor: Yosuke Takeuchi
  • Publication number: 20190006382
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 3, 2019
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Patent number: 10134796
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n?-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n?-type semiconductor region, and a p?-type semiconductor region formed between the n?-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n?-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p?-type semiconductor region is lower than a net impurity concentration in the p-type well.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Takeuchi, Tatsuya Kunikiyo
  • Patent number: 10062706
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 28, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yosuke Takeuchi, Eiji Tsukuda, Kenichiro Sonoda, Shibun Tsuda
  • Patent number: 10039187
    Abstract: A flexible substrate having a branch structure in the related art has problems in that: adhesive strength after two bodies are folded and fixed at a bonding region decreases due to an unfolding and opening force at a curve portion and ends of the bonded portions are peeled off and generate gaps; and in a soldering process of the two bodies, the electrodes of one body soldered first are displaced due to reheating in soldering the other body secondly and deteriorate in soldered connection. The present invention provides a new flexible substrate having a branch structure, including first and second bodies joined together, and having a structure in which one of the bodies can be folded back in a longitudinal direction of the whole flexible substrate. Tip ends of the two bodies are provided with multiple electrodes, and are connected by soldering to approximately corresponding positions on both surfaces of an end portion of a printed substrate concerned.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 31, 2018
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Kazumasa Yoshida, Toshiyuki Ozawa, Teruaki Sato, Atsushi Tomita, Yosuke Takeuchi, Shinji Mino, Yusuke Nasu
  • Publication number: 20180124920
    Abstract: A flexible substrate having a branch structure in the related art has problems in that: adhesive strength after two bodies are folded and fixed at a bonding region decreases due to an unfolding and opening force at a curve portion and ends of the bonded portions are peeled off and generate gaps; and in a soldering process of the two bodies, the electrodes of one body soldered first are displaced due to reheating in soldering the other body secondly and deteriorate in soldered connection. The present invention provides a new flexible substrate having a branch structure, including first and second bodies joined together, and having a structure in which one of the bodies can be folded back in a longitudinal direction of the whole flexible substrate. Tip ends of the two bodies are provided with multiple electrodes, and are connected by soldering to approximately corresponding positions on both surfaces of an end portion of a printed substrate concerned.
    Type: Application
    Filed: March 17, 2016
    Publication date: May 3, 2018
    Inventors: Kazumasa YOSHIDA, Toshiyuki OZAWA, Teruaki SATO, Atsushi TOMITA, Yosuke TAKEUCHI, Shinji MINO, Yusuke NASU
  • Publication number: 20180053804
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n?-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n?-type semiconductor region, and a p?-type semiconductor region formed between the n?-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n?-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p?-type semiconductor region is lower than a net impurity concentration in the p-type well.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yosuke TAKEUCHI, Tatsuya KUNIKIYO
  • Publication number: 20180013240
    Abstract: An electrical connector with a shielding plate in which signal terminals and ground terminals supported by insulating members are arranged in an intermixed order, signal terminals have at least a portion in the longitudinal direction thereof covered by a shielding plate, and respective contact portions formed in free end portions at the front ends of the signal terminals and ground terminals are subject to contact pressure applied by the corresponding counterpart terminals to one side of said contact portions, thereby resulting in resilient flexure, wherein in the shielding plate, at positions corresponding to the ground terminals in the direction of terminal array, there are provided grounding strips parallel to said ground terminals, said grounding strips extend forward and, at least in a state of contact between the ground terminals and counterpart terminals, the other side of the ground terminals is in contact with and supported by the grounding strips.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 11, 2018
    Inventor: Yosuke TAKEUCHI
  • Publication number: 20170358885
    Abstract: Example implementations involve an electrical connector and a test method of the electrical connector, wherein the electrical conduction condition between a ground member and a ground terminal can be easily confirmed while reliably contacting the ground member and ground terminal. Electrical connector involves a plurality of terminals including two types of terminals, namely, signal terminals and ground terminals; a retaining body, made of an insulating material, that arranges and retains the plurality of terminals in a condition where the signal terminals and ground terminals are intermingled; and a ground member retained by the retaining body on the inward side of the retaining body, in a condition contacting at least two ground terminals; wherein the ground member has a detecting part exposed from the retaining body in order to detect an electrical conduction condition between the ground terminals and the ground member.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 14, 2017
    Inventors: Takeshi OKUYAMA, Yosuke TAKEUCHI
  • Patent number: 9837460
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n?-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n?-type semiconductor region, and a p?-type semiconductor region formed between the n?-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n?-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p?-type semiconductor region is lower than a net impurity concentration in the p-type well.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Takeuchi, Tatsuya Kunikiyo
  • Publication number: 20170345842
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: August 21, 2017
    Publication date: November 30, 2017
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Patent number: 9780109
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 3, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yosuke Takeuchi, Eiji Tsukuda, Kenichiro Sonoda, Shibun Tsuda
  • Publication number: 20170186804
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n?-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n?-type semiconductor region, and a p?-type semiconductor region formed between the n?-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n?-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p?-type semiconductor region is lower than a net impurity concentration in the p-type well.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 29, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Yosuke TAKEUCHI, Tatsuya KUNIKIYO
  • Publication number: 20170084625
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Publication number: 20170018700
    Abstract: In a piezoelectric polymer composite in which piezoelectric particles are dispersed in a polymer matrix, the piezoelectric particles include 5 vol % to 30 vol % of particles having a particle size which is 0.25 times to 1 time a thickness of the piezoelectric polymer composite. As a result, the piezoelectric polymer composite exhibits satisfactory piezoelectric characteristics.
    Type: Application
    Filed: September 27, 2016
    Publication date: January 19, 2017
    Applicant: FUJIFILM Corporation
    Inventors: Tetsu MIYOSHI, Yosuke TAKEUCHI
  • Patent number: 9294826
    Abstract: A wavelength selection switch system includes a wavelength selection switch including an input port and an output port, a nonvolatile memory in which configuration information for controlling an operation of the wavelength selection switch is stored, a high-speed memory in which reading and writing can be performed at a higher speed than in the nonvolatile memory and that stores a copy of the configuration information stored in the nonvolatile memory, and a control unit that controls an operation of the wavelength selection switch based on the configuration information read from the high-speed memory, wherein the control unit periodically reads the configuration information stored in the nonvolatile memory and writes a copy of the read configuration information to the high-speed memory.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 22, 2016
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Tomoyoshi Kataoka, Mitsunori Fukutoku, Etsu Hashimoto, Akio Sahara, Norio Sato, Yosuke Takeuchi
  • Patent number: 9247324
    Abstract: A wavelength selection switch system includes a wavelength selection switch including an input port and an output port, a nonvolatile memory in which configuration information for controlling an operation of the wavelength selection switch is stored, a high-speed memory in which reading and writing can be performed at a higher speed than in the nonvolatile memory and that stores a copy of the configuration information stored in the nonvolatile memory, and a control unit that controls an operation of the wavelength selection switch based on the configuration information read from the high-speed memory, wherein the control unit periodically reads the configuration information stored in the nonvolatile memory and writes a copy of the read configuration information to the high-speed memory.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: January 26, 2016
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Tomoyoshi Kataoka, Mitsunori Fukutoku, Etsu Hashimoto, Akio Sahara, Norio Sato, Yosuke Takeuchi
  • Publication number: 20150030327
    Abstract: A wavelength selection switch system includes a wavelength selection switch including an input port and an output port, a nonvolatile memory in which configuration information for controlling an operation of the wavelength selection switch is stored, a high-speed memory in which reading and writing can be performed at a higher speed than in the nonvolatile memory and that stores a copy of the configuration information stored in the nonvolatile memory, and a control unit that controls an operation of the wavelength selection switch based on the configuration information read from the high-speed memory, wherein the control unit periodically reads the configuration information stored in the nonvolatile memory and writes a copy of the read configuration information to the high-speed memory.
    Type: Application
    Filed: February 5, 2013
    Publication date: January 29, 2015
    Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, NTT Electronics Corporation
    Inventors: Tomoyoshi Kataoka, Mitsunori Fukutoku, Etsu Hashimoto, Akio Sahara, Norio Sato, Yosuke Takeuchi